diff --git a/techlibs/analogdevices/brams.txt b/techlibs/analogdevices/brams.txt
index 9a5111490..f5c45aacf 100644
--- a/techlibs/analogdevices/brams.txt
+++ b/techlibs/analogdevices/brams.txt
@@ -1,56 +1,188 @@
-# family:        T16FFC            T40LP
-# BRAM:          RBRAM2            RBRAM
-# Supported:     SDP_8192x05       SDP_4096x05
-#                SDP_4096x10       SDP_2048x10
-#                SDP_2048x40       SDP_1024x40
-# Ignored:       SDP_4096x09       SDP_2048x09
-# Unimplemented: SP_2048x20        SP_1024x20
-#                TDP_4096x09
-#                TDP_8192x05
-#                TDP_2048x40
-#                SP2_2048x09       SP2_1024x09
-#                SP2_4096x05       SP2_2048x05
+ifdef IS_T16FFC {
+	ram block $__ANALOGDEVICES_BLOCKRAM_FULL_ {
+		option "ERR" "ECC" {
+			style "ECC";
+			option "SIZE" "2048x32" {
+				abits 11;
+				width 32;
+				byte 32;
+				option "MODE" "TDP" cost 2501;
+				option "MODE" "SDP" cost 2401;
+			}
+		}
+		option "ERR" "BP" {
+			style "BP";
+			option "SIZE" "2048x36" {
+				abits 11;
+				width 36;
+				byte 9;
+				option "MODE" "TDP" cost 2504;
+				option "MODE" "SDP" cost 2404;
+			}
+		}
+		option "ERR" "NONE" {
+			option "SIZE" "8192x05" {
+				abits 13;
+				width 5;
+				byte 1;
+				option "MODE" "TDP" cost 2505;
+				option "MODE" "SDP" cost 2405;
+			}
+			option "SIZE" "4096x09" {
+				abits 12;
+				width 9;
+				byte 1;
+				option "MODE" "TDP" cost 2509;
+				option "MODE" "SDP" cost 2409;
+			}
+			option "SIZE" "4096x10" {
+				abits 12;
+				width 10;
+				byte 1;
+				option "MODE" "TDP" forbid;
+				option "MODE" "SDP" cost 2410;
+			}
+			option "SIZE" "2048x40" {
+				abits 11;
+				width 40;
+				byte 8;
+				option "MODE" "TDP" cost 2505;
+				option "MODE" "SDP" cost 2405;
+			}
+		}
 
+		# supports any initialization value, but need to export memory files
+		init any;
 
-# Simple Dual Port
-
-ram block $__ANALOGDEVICES_BLOCKRAM_SDP_ {
-	option "ENABLE_WIDTH" "BIT" {
-		ifdef IS_T40LP {
-			abits 12;
+		option "MODE" "TDP" {
+			port srsw "A" {
+				clock anyedge;
+				clken;
+				rdwr no_change;
+			}
+			port srsw "B" {
+				clock anyedge;
+				clken;
+				rdwr no_change;
+			}
 		}
-		ifdef IS_T16FFC {
-			abits 13;
+		option "MODE" "SDP" {
+			port sw "A" {
+				clock anyedge;
+				clken;
+			}
+			port sr "B" {
+				clock anyedge;
+				clken;
+			}
 		}
-		widths 5 10 global;
-		byte 1;
-		cost 1;
-	}
-	option "ENABLE_WIDTH" "BYTE" {
-		ifdef IS_T40LP {
-			abits 10;
-		}
-		ifdef IS_T16FFC {
-			abits 11;
-		}
-		width 40;
-		byte 8;
-		cost 4;
-	}
-	# Unclear if/how RBRAM is initialized, default SIM_INIT_BEHAVIOUR is UNINITIALIZED
-	init none;
-	port sr "R" {
-		clock anyedge;
-		clken;
-	}
-	port sw "W" {
-		clock anyedge;
-		clken;
 	}
 }
 
-# Single Port
+ram block $__ANALOGDEVICES_BLOCKRAM_HALF_ {
+	option "ERR" "ECC" {
+		style "ECC";
+		option "SIZE" "1024x32" {
+			abits 10;
+			width 32;
+			byte 32;
+			option "MODE" "SDP" cost 2401;
+			option "MODE" "SP" cost 2301;
+		}
+	}
+	option "ERR" "BP" {
+		style "BP";
+		option "SIZE" "1024x36" {
+			abits 10;
+			width 36;
+			byte 9;
+			option "MODE" "SDP" cost 2404;
+			option "MODE" "SP" cost 2304;
+		}
+	}
+	option "ERR" "NONE" {
+		option "SIZE" "4096x05" {
+			abits 12;
+			width 5;
+			byte 1;
+			option "MODE" "SDP" cost 2405;
+			option "MODE" "SP" cost 2305;
+		}
+		option "SIZE" "2048x09" {
+			abits 11;
+			width 9;
+			byte 1;
+			option "MODE" "SDP" cost 2409;
+			option "MODE" "SP" cost 2309;
+		}
+		option "SIZE" "2048x10" {
+			abits 11;
+			width 10;
+			byte 1;
+			option "MODE" "SDP" cost 2410;
+			option "MODE" "SP" cost 2310;
+		}
+		option "SIZE" "1024x40" {
+			abits 10;
+			width 40;
+			byte 8;
+			option "MODE" "SDP" cost 2405;
+			option "MODE" "SP" cost 2305;
+		}
+	}
 
-# True Dual Port
+	option "MODE" "SDP" {
+		ifdef IS_T16FFC forbid;
+		port sw "A" {
+			clock anyedge;
+			clken;
+		}
+		port sr "B" {
+			clock anyedge;
+			clken;
+		}
+	}
+	option "MODE" "SP" {
+		ifdef IS_T40LP forbid;
+		port srsw "A" {
+			clock anyedge;
+			clken;
+			rdwr no_change;
+		}
+	}
+}
 
-# Dual Single Port
+ifdef IS_T40LP {
+	ram block $__ANALOGDEVICES_BLOCKRAM_QUARTER_ {
+		option "ERR" "BP" {
+			style "BP";
+			option "SIZE" "512x18" {
+				abits 9;
+				width 18;
+				byte 9;
+				option "MODE" "SP" cost 2202;
+			}
+		}
+		option "ERR" "NONE" {
+			option "SIZE" "2048x05" {
+				abits 11;
+				width 5;
+				byte 1;
+				option "MODE" "SP" cost 2205;
+			}
+			option "SIZE" "1024x09" {
+				abits 10;
+				width 9;
+				byte 1;
+				option "MODE" "SP" cost 2209;
+			}
+		}
+		option "MODE" "SP" {
+			port srsw "A" {
+				clock anyedge;
+				clken;
+				rdwr no_change;
+			}
+		}
+	}
+}
diff --git a/techlibs/analogdevices/brams_map.v b/techlibs/analogdevices/brams_map.v
index b2ba6b77d..c486670e3 100644
--- a/techlibs/analogdevices/brams_map.v
+++ b/techlibs/analogdevices/brams_map.v
@@ -1,78 +1,234 @@
-module $__ANALOGDEVICES_BLOCKRAM_SDP_ (...);
+module $__ANALOGDEVICES_BLOCKRAM_FULL_ (...);
+	// libmap params
+	parameter INIT = 0;
+	parameter OPTION_MODE = "NONE";
+	parameter OPTION_SIZE = "NONE";
+	parameter OPTION_ERR = "NONE";
+	parameter PORT_A_WR_EN_WIDTH = 1;
+	parameter PORT_A_CLK_POL = 1;
+	parameter PORT_B_WR_EN_WIDTH = 1;
+	parameter PORT_B_CLK_POL = 1;
 
-parameter INIT = 0;
-parameter OPTION_ENABLE_WIDTH = "BIT";
-parameter WIDTH = 40;
+	// needs -force-params
+	parameter WIDTH = 40;
+	parameter ABITS = 13;
 
+	// non libmap params
 `ifdef IS_T40LP
-parameter ABITS = 12;
-localparam NODE = "T40LP_Gen2.4";
-localparam BRAM_MODE = WIDTH ==  5 ? "SDP_4096x05" :
-	WIDTH == 10 ? "SDP_2048x10" : "SDP_1024x40";
-`elsif IS_T16FFC
-parameter ABITS = 13;
-localparam NODE = "T16FFC_Gen2.4";
-localparam BRAM_MODE = WIDTH ==  5 ? "SDP_8192x05" :
-	WIDTH == 10 ? "SDP_4096x10" : "SDP_2048x40";
-`endif
-
-parameter PORT_W_WR_EN_WIDTH = 5;
-parameter PORT_W_CLK_POL = 1;
-
-parameter PORT_R_CLK_POL = 1;
-
-input PORT_W_CLK;
-input PORT_W_CLK_EN;
-input [ABITS-1:0] PORT_W_ADDR;
-input [WIDTH-1:0] PORT_W_WR_DATA;
-input [PORT_W_WR_EN_WIDTH-1:0] PORT_W_WR_EN;
-
-input PORT_R_CLK;
-input PORT_R_CLK_EN;
-input [ABITS-1:0] PORT_R_ADDR;
-output [WIDTH-1:0] PORT_R_RD_DATA;
-
-`ifdef IS_T40LP
-RBRAM
+	localparam NODE = "T40LP_Gen2.4";
 `endif
 `ifdef IS_T16FFC
-RBRAM2
+	localparam NODE = "T16FFC_Gen2.4";
 `endif
-#(
-	.TARGET_NODE(NODE),
-	.BRAM_MODE(BRAM_MODE),
-	.QA_REG(0),
-	.QB_REG(0),
-	.CLKA_INV(!PORT_W_CLK_POL),
-	.CLKB_INV(!PORT_R_CLK_POL),
-	.DATA_WIDTH(WIDTH),
-	.ADDR_WIDTH(
-		WIDTH ==  5 ? ABITS :
-		WIDTH == 10 ? ABITS-1 : ABITS-2
-	),
-	.WE_WIDTH(OPTION_ENABLE_WIDTH == "BIT" ? WIDTH : PORT_W_WR_EN_WIDTH),
-	.PERR_WIDTH(1),
-)
-_TECHMAP_REPLACE_
-(
-	// .QA(0),
-	.DA(PORT_W_WR_DATA),
-	.CEA(PORT_W_CLK_EN),
-	.WEA(PORT_W_WR_EN),
-	.AA(
-		WIDTH ==  5 ? PORT_W_ADDR :
-		WIDTH == 10 ? PORT_W_ADDR[ABITS-1:1] : PORT_W_ADDR[ABITS-1:2]
-	),
-	.CLKA(PORT_W_CLK),
-	.QB(PORT_R_RD_DATA),
-	// .DB(0),
-	.CEB(PORT_R_CLK_EN),
-	// .WEB(0),
-	.AB(
-		WIDTH ==  5 ? PORT_R_ADDR :
-		WIDTH == 10 ? PORT_R_ADDR[ABITS-1:1] : PORT_R_ADDR[ABITS-1:2]
-	),
-	.CLKB(PORT_R_CLK),
-);
+	// localparam BRAM_MODE = "SDP_2048x36_BP";
+	localparam BRAM_MODE = (OPTION_ERR!="NONE") ? {OPTION_MODE, "_", OPTION_SIZE, "_", OPTION_ERR} :
+							{OPTION_MODE, "_", OPTION_SIZE};
+	localparam PBITS = 	(OPTION_ERR=="FP") ? 1 :
+						(OPTION_ERR=="BP") ? PORT_A_WR_EN_WIDTH :
+						0;
+
+	// libmap ports
+	input PORT_A_CLK;
+	input PORT_A_CLK_EN;
+	input [ABITS-1:0] PORT_A_ADDR;
+	input [WIDTH-1:0] PORT_A_WR_DATA;
+	output [WIDTH-1:0] PORT_A_RD_DATA;
+	input [PORT_A_WR_EN_WIDTH-1:0] PORT_A_WR_EN;
+
+	input PORT_B_CLK;
+	input PORT_B_CLK_EN;
+	input [ABITS-1:0] PORT_B_ADDR;
+	input [WIDTH-1:0] PORT_B_WR_DATA;
+	output [WIDTH-1:0] PORT_B_RD_DATA;
+	input [PORT_B_WR_EN_WIDTH-1:0] PORT_B_WR_EN;
+
+`ifdef IS_T40LP
+	RBRAM
+`endif
+`ifdef IS_T16FFC
+	RBRAM2
+`endif
+	#(
+		.TARGET_NODE(NODE),
+		.BRAM_MODE(BRAM_MODE),
+		.QA_REG(0),
+		.QB_REG(0),
+		.CLKA_INV(!PORT_A_CLK_POL),
+		.CLKB_INV(!PORT_B_CLK_POL),
+		.DATA_WIDTH(WIDTH),
+		.ADDR_WIDTH(ABITS),
+		.WE_WIDTH(PORT_A_WR_EN_WIDTH),
+		.PERR_WIDTH(PBITS),
+	)
+	_TECHMAP_REPLACE_
+	(
+		.QA(PORT_A_RD_DATA),
+		.DA(PORT_A_WR_DATA),
+		.CEA(PORT_A_CLK_EN),
+		.WEA(PORT_A_WR_EN),
+		.AA(PORT_A_ADDR),
+		.CLKA(PORT_A_CLK),
+		.QB(PORT_B_RD_DATA),
+		.DB(PORT_B_WR_DATA),
+		.CEB(PORT_B_CLK_EN),
+		.WEB(PORT_B_WR_EN),
+		.AB(PORT_B_ADDR),
+		.CLKB(PORT_B_CLK),
+	);
+
+	// check config
+	generate
+		case (BRAM_MODE)
+		`ifdef IS_T40LP
+			"SDP_1024x18_FP",
+			"SDP_1024x16_BP",
+			"SDP_2048x09",
+			"SDP_4096x05",
+			"SDP_1024x32_ECC",
+			"SDP_1024x40",
+			"SDP_1024x36_BP",
+			"SDP_512x32_ECC",
+			"SDP_512x36_BP",
+			"SDP_2048x10",
+			"SP_512x32_ECC",
+			"SP_512x36_BP",
+			"SP_1024x20",
+			"SP2_512x18_BP",
+			"SP2_1024x09",
+			"SP2_2048x05": wire _TECHMAP_FAIL_ = 0;
+		`endif
+		`ifdef IS_T16FFC
+			"TDP_2048x18_FP",
+			"TDP_2048x16_BP",
+			"TDP_4096x09",
+			"TDP_8192x05",
+			"TDP_2048x32_ECC",
+			"TDP_2048x40",
+			"TDP_2048x36_BP",
+			"SDP_2048x18_FP",
+			"SDP_2048x16_BP",
+			"SDP_4096x09",
+			"SDP_8192x05",
+			"SDP_2048x32_ECC",
+			"SDP_2048x40",
+			"SDP_2048x36_BP",
+			"SDP_1024x32_ECC",
+			"SDP_1024x36_BP",
+			"SDP_4096x10",
+			"SP_1024x32_ECC",
+			"SP_1024x36_BP",
+			"SP_2048x20",
+			"SP2_1024x18_BP",
+			"SP2_2048x09",
+			"SP2_4096x05": wire _TECHMAP_FAIL_ = 0;
+		`endif
+			default: wire _TECHMAP_FAIL_ = 1;
+		endcase
+	endgenerate
 
 endmodule
+
+module $__ANALOGDEVICES_BLOCKRAM_HALF_ (...);
+	// libmap params
+	parameter INIT = 0;
+	parameter OPTION_MODE = "NONE";
+	parameter OPTION_SIZE = "NONE";
+	parameter OPTION_ERR = "NONE";
+	parameter PORT_A_WR_EN_WIDTH = 1;
+	parameter PORT_A_CLK_POL = 1;
+	parameter PORT_B_WR_EN_WIDTH = 1;
+	parameter PORT_B_CLK_POL = 1;
+
+	// needs -force-params
+	parameter WIDTH = 40;
+	parameter ABITS = 13;
+
+	// libmap ports
+	input PORT_A_CLK;
+	input PORT_A_CLK_EN;
+	input [ABITS-1:0] PORT_A_ADDR;
+	input [WIDTH-1:0] PORT_A_WR_DATA;
+	output [WIDTH-1:0] PORT_A_RD_DATA;
+	input [PORT_A_WR_EN_WIDTH-1:0] PORT_A_WR_EN;
+
+	input PORT_B_CLK;
+	input PORT_B_CLK_EN;
+	input [ABITS-1:0] PORT_B_ADDR;
+	input [WIDTH-1:0] PORT_B_WR_DATA;
+	output [WIDTH-1:0] PORT_B_RD_DATA;
+	input [PORT_B_WR_EN_WIDTH-1:0] PORT_B_WR_EN;
+
+	$__ANALOGDEVICES_BLOCKRAM_FULL_
+	# (
+		.INIT(INIT),
+		.OPTION_MODE(OPTION_MODE),
+		.OPTION_SIZE(OPTION_SIZE),
+		.PORT_A_WR_EN_WIDTH(PORT_A_WR_EN_WIDTH),
+		.PORT_A_CLK_POL(PORT_A_CLK_POL),
+		.PORT_B_WR_EN_WIDTH(PORT_B_WR_EN_WIDTH),
+		.PORT_B_CLK_POL(PORT_B_CLK_POL),
+		.WIDTH(WIDTH),
+		.ABITS(ABITS)
+	)
+	_TECHMAP_REPLACE_
+	(
+		.PORT_A_CLK(PORT_A_CLK),
+		.PORT_A_CLK_EN(PORT_A_CLK_EN),
+		.PORT_A_ADDR(PORT_A_ADDR),
+		.PORT_A_WR_DATA(PORT_A_WR_DATA),
+		.PORT_A_RD_DATA(PORT_A_RD_DATA),
+		.PORT_A_WR_EN(PORT_A_WR_EN),
+		.PORT_B_CLK(PORT_B_CLK),
+		.PORT_B_CLK_EN(PORT_B_CLK_EN),
+		.PORT_B_ADDR(PORT_B_ADDR),
+		.PORT_B_WR_DATA(PORT_B_WR_DATA),
+		.PORT_B_RD_DATA(PORT_B_RD_DATA),
+		.PORT_B_WR_EN(PORT_B_WR_EN)
+	);
+endmodule
+
+module $__ANALOGDEVICES_BLOCKRAM_QUARTER_ (...);
+	// libmap params
+	parameter INIT = 0;
+	parameter OPTION_MODE = "NONE";
+	parameter OPTION_SIZE = "NONE";
+	parameter OPTION_ERR = "NONE";
+	parameter PORT_A_WR_EN_WIDTH = 1;
+	parameter PORT_A_CLK_POL = 1;
+	parameter PORT_B_WR_EN_WIDTH = 1;
+	parameter PORT_B_CLK_POL = 1;
+
+	// needs -force-params
+	parameter WIDTH = 40;
+	parameter ABITS = 13;
+
+	// libmap ports
+	input PORT_A_CLK;
+	input PORT_A_CLK_EN;
+	input [ABITS-1:0] PORT_A_ADDR;
+	input [WIDTH-1:0] PORT_A_WR_DATA;
+	output [WIDTH-1:0] PORT_A_RD_DATA;
+	input [PORT_A_WR_EN_WIDTH-1:0] PORT_A_WR_EN;
+
+	$__ANALOGDEVICES_BLOCKRAM_FULL_
+	# (
+		.INIT(INIT),
+		.OPTION_MODE(OPTION_MODE),
+		.OPTION_SIZE(OPTION_SIZE),
+		.PORT_A_WR_EN_WIDTH(PORT_A_WR_EN_WIDTH),
+		.PORT_A_CLK_POL(PORT_A_CLK_POL),
+		.PORT_B_WR_EN_WIDTH(PORT_B_WR_EN_WIDTH),
+		.PORT_B_CLK_POL(PORT_B_CLK_POL),
+		.WIDTH(WIDTH),
+		.ABITS(ABITS)
+	)
+	_TECHMAP_REPLACE_
+	(
+		.PORT_A_CLK(PORT_A_CLK),
+		.PORT_A_CLK_EN(PORT_A_CLK_EN),
+		.PORT_A_ADDR(PORT_A_ADDR),
+		.PORT_A_WR_DATA(PORT_A_WR_DATA),
+		.PORT_A_RD_DATA(PORT_A_RD_DATA),
+		.PORT_A_WR_EN(PORT_A_WR_EN),
+	);
+endmodule
diff --git a/techlibs/analogdevices/lutrams.txt b/techlibs/analogdevices/lutrams.txt
index 804b78252..a52c28171 100644
--- a/techlibs/analogdevices/lutrams.txt
+++ b/techlibs/analogdevices/lutrams.txt
@@ -1,39 +1,20 @@
-# Single-port RAMs.
-
-ram distributed $__ANALOGDEVICES_LUTRAM_SP_ {
-	option "ABITS" 5 {
-		cost 1;
-		abits 5;
-	}
-	option "ABITS" 6 {
-		cost 2;
-		abits 6;
-	}
+ram distributed $__ANALOGDEVICES_LUTRAM_ {
+	option "SIZE" 32 abits 5;
+	option "SIZE" 64 abits 6;
 	width 1;
 	init no_undef;
 	prune_rom;
 	port arsw "RW" {
 		clock posedge;
 	}
-}
-
-# Dual-port RAMs.
-
-ram distributed $__ANALOGDEVICES_LUTRAM_DP_ {
-	option "ABITS" 5 {
-		cost 2;
-		abits 5;
+	option "MODE" "SP" {
+		option "SIZE" 32 cost 1;
+		option "SIZE" 64 cost 2;
 	}
-	option "ABITS" 6 {
-		cost 4;
-		abits 6;
-	}
-	width 1;
-	init no_undef;
-	prune_rom;
-	port arsw "RW" {
-		clock posedge;
-	}
-	port ar "R" {
+	option "MODE" "DP" {
+		option "SIZE" 32 cost 2;
+		option "SIZE" 64 cost 4;
+		port ar "R" {
+		}
 	}
 }
diff --git a/techlibs/analogdevices/lutrams_map.v b/techlibs/analogdevices/lutrams_map.v
index 7962e616c..18fa93516 100644
--- a/techlibs/analogdevices/lutrams_map.v
+++ b/techlibs/analogdevices/lutrams_map.v
@@ -1,54 +1,116 @@
-module $__ANALOGDEVICES_LUTRAM_SP_ (...);
+module $__ANALOGDEVICES_LUTRAM_ (...);
 
 parameter INIT = 0;
-parameter OPTION_ABITS = 5;
+parameter OPTION_SIZE = 32;
+parameter OPTION_MODE = "SP";
+parameter ABITS = 5;
+parameter WIDTH = 1;
 
 output PORT_RW_RD_DATA;
 input PORT_RW_WR_DATA;
-input [OPTION_ABITS-1:0] PORT_RW_ADDR;
+input [ABITS-1:0] PORT_RW_ADDR;
 input PORT_RW_WR_EN;
 input PORT_RW_CLK;
 
+output PORT_R_RD_DATA;
+input [ABITS-1:0] PORT_R_ADDR;
+
 generate
-case(OPTION_ABITS)
-5:
-	RAMS32X1
-	#(
-		.INIT(INIT)
-	)
-	_TECHMAP_REPLACE_
-	(
-		.O(PORT_RW_RD_DATA),
-		.A0(PORT_RW_ADDR[0]),
-		.A1(PORT_RW_ADDR[1]),
-		.A2(PORT_RW_ADDR[2]),
-		.A3(PORT_RW_ADDR[3]),
-		.A4(PORT_RW_ADDR[4]),
-		.D(PORT_RW_WR_DATA),
-		.WCLK(PORT_RW_CLK),
-		.WE(PORT_RW_WR_EN)
-	);
-6:
-	RAMS64X1
-	#(
-		.INIT(INIT)
-	)
-	_TECHMAP_REPLACE_
-	(
-		.O(PORT_RW_RD_DATA),
-		.A0(PORT_RW_ADDR[0]),
-		.A1(PORT_RW_ADDR[1]),
-		.A2(PORT_RW_ADDR[2]),
-		.A3(PORT_RW_ADDR[3]),
-		.A4(PORT_RW_ADDR[4]),
-		.A5(PORT_RW_ADDR[5]),
-		.D(PORT_RW_WR_DATA),
-		.WCLK(PORT_RW_CLK),
-		.WE(PORT_RW_WR_EN)
-	);
-default:
-	$error("invalid OPTION_ABITS");
-endcase
+	if (OPTION_MODE=="SP")
+	case(OPTION_SIZE)
+	32:
+		RAMS32X1
+		#(
+			.INIT(INIT)
+		)
+		_TECHMAP_REPLACE_
+		(
+			.O(PORT_RW_RD_DATA),
+			.A0(PORT_RW_ADDR[0]),
+			.A1(PORT_RW_ADDR[1]),
+			.A2(PORT_RW_ADDR[2]),
+			.A3(PORT_RW_ADDR[3]),
+			.A4(PORT_RW_ADDR[4]),
+			.D(PORT_RW_WR_DATA),
+			.WCLK(PORT_RW_CLK),
+			.WE(PORT_RW_WR_EN)
+		);
+	64:
+		RAMS64X1
+		#(
+			.INIT(INIT)
+		)
+		_TECHMAP_REPLACE_
+		(
+			.O(PORT_RW_RD_DATA),
+			.A0(PORT_RW_ADDR[0]),
+			.A1(PORT_RW_ADDR[1]),
+			.A2(PORT_RW_ADDR[2]),
+			.A3(PORT_RW_ADDR[3]),
+			.A4(PORT_RW_ADDR[4]),
+			.A5(PORT_RW_ADDR[5]),
+			.D(PORT_RW_WR_DATA),
+			.WCLK(PORT_RW_CLK),
+			.WE(PORT_RW_WR_EN)
+		);
+	default:
+		$error("invalid SIZE/MODE combination");
+	endcase
+	else if (OPTION_MODE=="DP")
+	case (OPTION_SIZE)
+	32:
+		RAMD32X1
+		#(
+			.INIT(INIT)
+		)
+		_TECHMAP_REPLACE_
+		(
+			.DPO(PORT_R_RD_DATA),
+			.SPO(PORT_RW_RD_DATA),
+			.A0(PORT_RW_ADDR[0]),
+			.A1(PORT_RW_ADDR[1]),
+			.A2(PORT_RW_ADDR[2]),
+			.A3(PORT_RW_ADDR[3]),
+			.A4(PORT_RW_ADDR[4]),
+			.D(PORT_RW_WR_DATA),
+			.DPRA0(PORT_R_ADDR[0]),
+			.DPRA1(PORT_R_ADDR[1]),
+			.DPRA2(PORT_R_ADDR[2]),
+			.DPRA3(PORT_R_ADDR[3]),
+			.DPRA4(PORT_R_ADDR[4]),
+			.WCLK(PORT_RW_CLK),
+			.WE(PORT_RW_WR_EN)
+		);
+	64:
+		RAMD64X1
+		#(
+			.INIT(INIT)
+		)
+		_TECHMAP_REPLACE_
+		(
+			.DPO(PORT_R_RD_DATA),
+			.SPO(PORT_RW_RD_DATA),
+			.A0(PORT_RW_ADDR[0]),
+			.A1(PORT_RW_ADDR[1]),
+			.A2(PORT_RW_ADDR[2]),
+			.A3(PORT_RW_ADDR[3]),
+			.A4(PORT_RW_ADDR[4]),
+			.A5(PORT_RW_ADDR[5]),
+			.D(PORT_RW_WR_DATA),
+			.DPRA0(PORT_R_ADDR[0]),
+			.DPRA1(PORT_R_ADDR[1]),
+			.DPRA2(PORT_R_ADDR[2]),
+			.DPRA3(PORT_R_ADDR[3]),
+			.DPRA4(PORT_R_ADDR[4]),
+			.DPRA5(PORT_R_ADDR[5]),
+			.WCLK(PORT_RW_CLK),
+			.WE(PORT_RW_WR_EN)
+		);
+	default:
+		$error("invalid SIZE/MODE combination");
+	endcase
+	else
+		wire _TECHMAP_FAIL_ = 1;
 endgenerate
 
 endmodule
@@ -57,70 +119,21 @@ endmodule
 module $__ANALOGDEVICES_LUTRAM_DP_ (...);
 
 parameter INIT = 0;
-parameter OPTION_ABITS = 5;
+parameter OPTION_SIZE = 32;
+parameter ABITS = 5;
+parameter WIDTH = 1;
 
 output PORT_RW_RD_DATA;
 input PORT_RW_WR_DATA;
-input [OPTION_ABITS-1:0] PORT_RW_ADDR;
+input [ABITS-1:0] PORT_RW_ADDR;
 input PORT_RW_WR_EN;
 input PORT_RW_CLK;
 
 output PORT_R_RD_DATA;
-input [OPTION_ABITS-1:0] PORT_R_ADDR;
+input [ABITS-1:0] PORT_R_ADDR;
 
 generate
-case (OPTION_ABITS)
-5: 
-	RAMD32X1
-	#(
-		.INIT(INIT)
-	)
-	_TECHMAP_REPLACE_
-	(
-		.DPO(PORT_R_RD_DATA),
-		.SPO(PORT_RW_RD_DATA),
-		.A0(PORT_RW_ADDR[0]),
-		.A1(PORT_RW_ADDR[1]),
-		.A2(PORT_RW_ADDR[2]),
-		.A3(PORT_RW_ADDR[3]),
-		.A4(PORT_RW_ADDR[4]),
-		.D(PORT_RW_WR_DATA),
-		.DPRA0(PORT_R_ADDR[0]),
-		.DPRA1(PORT_R_ADDR[1]),
-		.DPRA2(PORT_R_ADDR[2]),
-		.DPRA3(PORT_R_ADDR[3]),
-		.DPRA4(PORT_R_ADDR[4]),
-		.WCLK(PORT_RW_CLK),
-		.WE(PORT_RW_WR_EN)
-	);
-6:
-	RAMD64X1
-	#(
-		.INIT(INIT)
-	)
-	_TECHMAP_REPLACE_
-	(
-		.DPO(PORT_R_RD_DATA),
-		.SPO(PORT_RW_RD_DATA),
-		.A0(PORT_RW_ADDR[0]),
-		.A1(PORT_RW_ADDR[1]),
-		.A2(PORT_RW_ADDR[2]),
-		.A3(PORT_RW_ADDR[3]),
-		.A4(PORT_RW_ADDR[4]),
-		.A5(PORT_RW_ADDR[5]),
-		.D(PORT_RW_WR_DATA),
-		.DPRA0(PORT_R_ADDR[0]),
-		.DPRA1(PORT_R_ADDR[1]),
-		.DPRA2(PORT_R_ADDR[2]),
-		.DPRA3(PORT_R_ADDR[3]),
-		.DPRA4(PORT_R_ADDR[4]),
-		.DPRA5(PORT_R_ADDR[5]),
-		.WCLK(PORT_RW_CLK),
-		.WE(PORT_RW_WR_EN)
-	);
-default:
-	$error("invalid OPTION_ABITS/WIDTH combination");
-endcase
+
 endgenerate
 
 endmodule
diff --git a/techlibs/analogdevices/synth_analogdevices.cc b/techlibs/analogdevices/synth_analogdevices.cc
index 18619de7a..8a41408c8 100644
--- a/techlibs/analogdevices/synth_analogdevices.cc
+++ b/techlibs/analogdevices/synth_analogdevices.cc
@@ -355,10 +355,9 @@ struct SynthAnalogDevicesPass : public ScriptPass
 				params = " [...]";
 			} else {
 				params += " -logic-cost-rom 0.015625";
+				params += " -force-params";
 				params += " -lib +/analogdevices/lutrams.txt";
-				lutrams_map = "+/analogdevices/lutrams_map.v";
 				params += " -lib +/analogdevices/brams.txt";
-				brams_map = "+/analogdevices/brams_map.v";
 				params += tech_param;
 				brams_map += tech_param;
 				if (nolutram)