mirror of
https://github.com/YosysHQ/yosys
synced 2025-07-24 21:27:00 +00:00
Merge remote-tracking branch 'origin/master' into eddie/xilinx_srl
This commit is contained in:
commit
6e475484b2
18 changed files with 262 additions and 137 deletions
|
@ -380,9 +380,10 @@ endmodule
|
|||
|
||||
module SRL16E (
|
||||
output Q,
|
||||
input A0, A1, A2, A3, CE,
|
||||
(* clkbuf_sink *)
|
||||
input CLK,
|
||||
input A0, A1, A2, A3, CE, D
|
||||
input D
|
||||
);
|
||||
parameter [15:0] INIT = 16'h0000;
|
||||
parameter [0:0] IS_CLK_INVERTED = 1'b0;
|
||||
|
@ -401,7 +402,10 @@ endmodule
|
|||
module SRLC16E (
|
||||
output Q,
|
||||
output Q15,
|
||||
input A0, A1, A2, A3, CE, CLK, D
|
||||
input A0, A1, A2, A3, CE,
|
||||
(* clkbuf_sink *)
|
||||
input CLK,
|
||||
input D
|
||||
);
|
||||
parameter [15:0] INIT = 16'h0000;
|
||||
parameter [0:0] IS_CLK_INVERTED = 1'b0;
|
||||
|
@ -422,9 +426,10 @@ module SRLC32E (
|
|||
output Q,
|
||||
output Q31,
|
||||
input [4:0] A,
|
||||
input CE,
|
||||
(* clkbuf_sink *)
|
||||
input CLK,
|
||||
input CE, D
|
||||
input D
|
||||
);
|
||||
parameter [31:0] INIT = 32'h00000000;
|
||||
parameter [0:0] IS_CLK_INVERTED = 1'b0;
|
||||
|
|
Loading…
Add table
Add a link
Reference in a new issue