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Merge pull request #1486 from YosysHQ/clifford/fsmdetectfix

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Bugfix in fsm_detect
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Clifford Wolf 2019-11-13 12:34:27 +01:00 committed by GitHub
parent e0ba78bdf2 4be5a0fd7c
commit 6e332161db
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GPG key ID: 4AEE18F83AFDEB23
1 changed files with 10 additions and 6 deletions
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16
passes/fsm/fsm_detect.cc
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@ -158,22 +158,25 @@ static void detect_fsm(RTLIL::Wire *wire)
std::set<sig2driver_entry_t> cellport_list; std::set<sig2driver_entry_t> cellport_list;
sig2user.find(sig_q, cellport_list); sig2user.find(sig_q, cellport_list);
auto sig_q_bits = sig_q.to_sigbit_pool();
for (auto &cellport : cellport_list) for (auto &cellport : cellport_list)
{ {
RTLIL::Cell *cell = cellport.first; RTLIL::Cell *cell = cellport.first;
bool set_output = false, clr_output = false; bool set_output = false, clr_output = false;
if (cell->type == "$ne") if (cell->type.in("$ne", "$reduce_or", "$reduce_bool"))
set_output = true; set_output = true;
if (cell->type == "$eq") if (cell->type.in("$eq", "$logic_not", "$reduce_and"))
clr_output = true; clr_output = true;
if (!set_output && !clr_output) { if (set_output || clr_output) {
clr_output = true;
for (auto &port_it : cell->connections()) for (auto &port_it : cell->connections())
if (port_it.first != "\\A" || port_it.first != "\\Y") if (cell->input(port_it.first))
clr_output = false; for (auto bit : assign_map(port_it.second))
if (bit.wire != nullptr && !sig_q_bits.count(bit))
goto next_cellport;
} }
if (set_output || clr_output) { if (set_output || clr_output) {
@ -184,6 +187,7 @@ static void detect_fsm(RTLIL::Wire *wire)
ce.set(sig, val); ce.set(sig, val);
} }
} }
next_cellport:;
} }
SigSpec sig_y = sig_d, sig_undef; SigSpec sig_y = sig_d, sig_undef;