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Started writing appnote 011

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Clifford Wolf 2013-11-28 13:48:38 +01:00
parent 5af7f4db72
commit 6dfb66d262
7 changed files with 157 additions and 3 deletions
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3
manual/APPNOTE_011_Design_Investigation/.gitignore vendored Normal file
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example_00.dot
example_01.dot
example_02.dot

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manual/APPNOTE_011_Design_Investigation/example.v Normal file
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module example(input clk, a, b, c, output reg [1:0] y);
always @(posedge clk)
if (c)
y <= c ? a + b : 2'd0;
endmodule

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manual/APPNOTE_011_Design_Investigation/example.ys Normal file
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read_verilog example.v
show -format dot -prefix example_00
proc
show -format dot -prefix example_01
opt
show -format dot -prefix example_02

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manual/APPNOTE_011_Design_Investigation/make.sh Normal file
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#!/bin/bash
../../yosys example.ys
sed -i '/^label=/ d;' example_*.dot
dot -Tpdf -o example_00.pdf example_00.dot
dot -Tpdf -o example_01.pdf example_01.dot
dot -Tpdf -o example_02.pdf example_02.dot