3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-23 00:55:32 +00:00

bug fix and cleanups

This commit is contained in:
Miodrag Milanovic 2022-02-04 10:01:06 +01:00
parent 7ef6da4c7d
commit 6db23de7b1
3 changed files with 8 additions and 8 deletions

View file

@ -1,9 +1,9 @@
read_verilog grom_computer.v grom_cpu.v alu.v ram_memory.v;
prep -top grom_computer;
sim -clock clk -reset reset -fst grom.fst -vcd grom.vcd -a -n 80
sim -clock clk -reset reset -fst grom.fst -vcd grom.vcd -n 80
sim -clock clk -r grom.fst -scope grom_computer -start 25ns -stop 100ns -sim-cmp
sim -clock clk -r grom.fst -scope grom_computer -stop 100ns -sim-gold
sim -clock clk -r grom.fst -scope grom_computer -n 10 -sim-gate -a
sim -clock clk -r grom.fst -scope grom_computer -n 10 -sim-gate