mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-07-24 05:08:56 +00:00
Code Activity

substr() -> compare()

Browse source
This commit is contained in:
Eddie Hung 2019-08-07 12:20:08 -07:00
parent 71eff6f0de
commit 6d77236f38
31 changed files with 127 additions and 127 deletions
Download patch file Download diff file Expand all files Collapse all files

6
passes/techmap/dff2dffe.cc
View file

@ -377,7 +377,7 @@ struct Dff2dffePass : public Pass {
mod->remove(cell);
continue;
}
if (cell->type.substr(0, 7) == "$_DFFE_") {
if (cell->type.begins_with("$_DFFE_")) {
if (min_ce_use >= 0) {
int ce_use = 0;
for (auto cell_other : mod->selected_cells()) {
@ -390,8 +390,8 @@ struct Dff2dffePass : public Pass {
continue;
}
bool clk_pol = cell->type.substr(7, 1) == "P";
bool en_pol = cell->type.substr(8, 1) == "P";
bool clk_pol = cell->type.compare(7, 1, "P") == 0;
bool en_pol = cell->type.compare(8, 1, "P") == 0;
RTLIL::SigSpec tmp = mod->addWire(NEW_ID);
mod->addDff(NEW_ID, cell->getPort("\\C"), tmp, cell->getPort("\\Q"), clk_pol);
if (en_pol)