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https://github.com/YosysHQ/yosys
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More comments, cleanup
This commit is contained in:
Eddie Hung
parent
7de9c33931
commit
6d68972619
2 changed files with 109 additions and 42 deletions
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@ -425,22 +425,42 @@ endcode
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// #######################
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// Subpattern for matching against input registers, based on knowledge of the
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// 'Q' input.
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// At a high level:
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// (1) Starting from a $dff cell that (partially or fully) drives the given
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// 'Q' argument
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// (2) Match for a $mux cell implementing synchronous reset semantics ---
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// one that exclusively drives the 'D' input of the $dff, with one of its
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// $mux inputs being fully zero
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// (3) Match for a $mux cell implement clock enable semantics --- one that
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// exclusively drives the 'D' input of the $dff (or the other input of
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// the reset $mux) and where one of this $mux's inputs is connected to
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// the 'Q' output of the $dff
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subpattern in_dffe
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arg argD argQ clock
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code
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dff = nullptr;
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for (auto c : argQ.chunks()) {
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for (const auto &c : argQ.chunks()) {
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// Abandon matches when 'Q' is a constant
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if (!c.wire)
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reject;
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// Abandon matches when 'Q' has the keep attribute set
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if (c.wire->get_bool_attribute(\keep))
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reject;
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Const init = c.wire->attributes.at(\init, State::Sx);
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if (!init.is_fully_undef() && !init.is_fully_zero())
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reject;
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// Abandon matches when 'Q' has a non-zero init attribute set
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// (not supported by DSP48E1)
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Const init = c.wire->attributes.at(\init, Const());
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if (!init.empty())
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for (auto b : init.extract(c.offset, c.width))
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if (b != State::Sx && b != State::S0)
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reject;
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}
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endcode
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// (1) Starting from a $dff cell that (partially or fully) drives the given
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// 'Q' argument
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match ff
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select ff->type.in($dff)
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// DSP48E1 does not support clock inversion
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@ -453,14 +473,12 @@ match ff
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filter GetSize(port(ff, \Q)) >= offset + GetSize(argQ)
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filter port(ff, \Q).extract(offset, GetSize(argQ)) == argQ
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filter clock == SigBit() || port(ff, \CLK) == clock
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set ffoffset offset
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endmatch
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code argQ argD
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{
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if (clock != SigBit() && port(ff, \CLK) != clock)
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reject;
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SigSpec Q = port(ff, \Q);
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dff = ff;
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dffclock = port(ff, \CLK);
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@ -472,9 +490,11 @@ code argQ argD
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// has two (ff, ffrstmux) users
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if (nusers(dffD) > 2)
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argD = SigSpec();
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}
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endcode
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// (2) Match for a $mux cell implementing synchronous reset semantics ---
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// exclusively drives the 'D' input of the $dff, with one of the $mux
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// inputs being fully zero
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match ffrstmux
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if !argD.empty()
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select ffrstmux->type.in($mux)
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@ -506,6 +526,10 @@ code argD
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dffrstmux = nullptr;
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endcode
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// (3) Match for a $mux cell implement clock enable semantics --- one that
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// exclusively drives the 'D' input of the $dff (or the other input of
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// the reset $mux) and where one of this $mux's inputs is connected to
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// the 'Q' output of the $dff
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match ffcemux
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if !argD.empty()
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select ffcemux->type.in($mux)
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@ -530,16 +554,32 @@ endcode
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// #######################
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// Subpattern for matching against output registers, based on knowledge of the
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// 'D' input.
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// At a high level:
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// (1) Starting from an optional $mux cell that implements clock enable
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// semantics --- one where the given 'D' argument (partially or fully)
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// drives one of its two inputs
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// (2) Starting from, or continuing onto, another optional $mux cell that
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// implements synchronous reset semantics --- one where the given 'D'
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// argument (or the clock enable $mux output) drives one of its two inputs
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// and where the other input is fully zero
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// (3) Match for a $dff cell (whose 'D' input is the 'D' argument, or the
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// output of the previous clock enable or reset $mux cells)
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subpattern out_dffe
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arg argD argQ clock
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code
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dff = nullptr;
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for (auto c : argD.chunks())
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// Abandon matches when 'D' has the keep attribute set
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if (c.wire->get_bool_attribute(\keep))
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reject;
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endcode
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// (1) Starting from an optional $mux cell that implements clock enable
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// semantics --- one where the given 'D' argument (partially or fully)
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// drives one of its two inputs
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match ffcemux
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select ffcemux->type.in($mux)
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// ffcemux output must have two users: ffcemux and ff.D
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@ -578,6 +618,10 @@ code argD argQ
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}
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endcode
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// (2) Starting from, or continuing onto, another optional $mux cell that
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// implements synchronous reset semantics --- one where the given 'D'
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// argument (or the clock enable $mux output) drives one of its two inputs
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// and where the other input is fully zero
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match ffrstmux
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select ffrstmux->type.in($mux)
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// ffrstmux output must have two users: ffrstmux and ff.D
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@ -616,6 +660,8 @@ code argD argQ
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}
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endcode
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// (3) Match for a $dff cell (whose 'D' input is the 'D' argument, or the
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// output of the previous clock enable or reset $mux cells)
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match ff
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select ff->type.in($dff)
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// DSP48E1 does not support clock inversion
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@ -632,32 +678,30 @@ match ff
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// Check that FF.Q is connected to CE-mux
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filter !ffcemux || port(ff, \Q).extract(offset, GetSize(argQ)) == argQ
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filter clock == SigBit() || port(ff, \CLK) == clock
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set ffoffset offset
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endmatch
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code argQ
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if (ff) {
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if (clock != SigBit() && port(ff, \CLK) != clock)
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reject;
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SigSpec D = port(ff, \D);
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SigSpec Q = port(ff, \Q);
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if (!ffcemux) {
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argQ = argD;
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argQ.replace(D, Q);
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}
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for (auto c : argQ.chunks()) {
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Const init = c.wire->attributes.at(\init, State::Sx);
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if (!init.is_fully_undef() && !init.is_fully_zero())
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reject;
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}
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dff = ff;
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dffQ = argQ;
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dffclock = port(ff, \CLK);
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SigSpec D = port(ff, \D);
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SigSpec Q = port(ff, \Q);
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if (!ffcemux) {
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argQ = argD;
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argQ.replace(D, Q);
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}
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// No enable/reset mux possible without flop
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else if (dffcemux || dffrstmux)
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reject;
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// Abandon matches when 'Q' has a non-zero init attribute set
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// (not supported by DSP48E1)
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for (auto c : argQ.chunks()) {
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Const init = c.wire->attributes.at(\init, Const());
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if (!init.empty())
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for (auto b : init.extract(c.offset, c.width))
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if (b != State::Sx && b != State::S0)
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reject;
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}
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dff = ff;
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dffQ = argQ;
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dffclock = port(ff, \CLK);
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endcode
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@ -77,7 +77,7 @@ endcode
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// (2) Match the driver of the 'C' input to a possible $dff cell (CREG)
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// (attached to at most two $mux cells that implement clock-enable or
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// reset functionality, using a subpattern discussed below)
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// reset functionality, using the in_dffe subpattern)
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code argQ ffC ffCcemux ffCrstmux ffCcepol ffCrstpol sigC clock
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argQ = sigC;
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subpattern(in_dffe);
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@ -103,22 +103,41 @@ endcode
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// #######################
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// Subpattern for matching against input registers, based on knowledge of the
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// 'Q' input.
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// At a high level:
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// (1) Starting from a $dff cell that (partially or fully) drives the given
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// 'Q' argument
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// (2) Match for a $mux cell implementing synchronous reset semantics ---
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// one that exclusively drives the 'D' input of the $dff, with one of its
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// $mux inputs being fully zero
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// (3) Match for a $mux cell implement clock enable semantics --- one that
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// exclusively drives the 'D' input of the $dff (or the other input of
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// the reset $mux) and where one of this $mux's inputs is connected to
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// the 'Q' output of the $dff
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subpattern in_dffe
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arg argD argQ clock
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code
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dff = nullptr;
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for (auto c : argQ.chunks()) {
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for (const auto &c : argQ.chunks()) {
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// Abandon matches when 'Q' is a constant
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if (!c.wire)
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reject;
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// Abandon matches when 'Q' has the keep attribute set
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if (c.wire->get_bool_attribute(\keep))
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reject;
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Const init = c.wire->attributes.at(\init, State::Sx);
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if (!init.is_fully_undef() && !init.is_fully_zero())
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reject;
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// Abandon matches when 'Q' has a non-zero init attribute set
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// (not supported by DSP48E1)
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Const init = c.wire->attributes.at(\init, Const());
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for (auto b : init.extract(c.offset, c.width))
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if (b != State::Sx && b != State::S0)
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reject;
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}
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endcode
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// (1) Starting from a $dff cell that (partially or fully) drives the given
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// 'Q' argument
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match ff
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select ff->type.in($dff)
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// DSP48E1 does not support clock inversion
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@ -131,14 +150,12 @@ match ff
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filter GetSize(port(ff, \Q)) >= offset + GetSize(argQ)
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filter port(ff, \Q).extract(offset, GetSize(argQ)) == argQ
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filter clock == SigBit() || port(ff, \CLK) == clock
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set ffoffset offset
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endmatch
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code argQ argD
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{
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if (clock != SigBit() && port(ff, \CLK) != clock)
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reject;
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SigSpec Q = port(ff, \Q);
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dff = ff;
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dffclock = port(ff, \CLK);
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@ -150,9 +167,11 @@ code argQ argD
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// has two (ff, ffrstmux) users
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if (nusers(dffD) > 2)
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argD = SigSpec();
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}
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endcode
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// (2) Match for a $mux cell implementing synchronous reset semantics ---
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// exclusively drives the 'D' input of the $dff, with one of the $mux
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// inputs being fully zero
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match ffrstmux
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if !argD.empty()
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select ffrstmux->type.in($mux)
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@ -184,6 +203,10 @@ code argD
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dffrstmux = nullptr;
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endcode
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// (3) Match for a $mux cell implement clock enable semantics --- one that
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// exclusively drives the 'D' input of the $dff (or the other input of
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// the reset $mux) and where one of this $mux's inputs is connected to
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// the 'Q' output of the $dff
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match ffcemux
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if !argD.empty()
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select ffcemux->type.in($mux)
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