Merge branch 'master' of github.com:YosysHQ/yosys into claire/eqystuff

tests/svtypes/struct_array.sv

@@ -81,6 +81,66 @@ module top;
 
 	always_comb assert(s3_b==80'hFC00_4200_0012_3400_FFFC);
 
+	struct packed {
+		bit [0:7] [0:1] [0:3] a;
+		bit [0:15] b;		// filler for non-zero offset
+	} s3_lll;
+
+	initial begin
+		s3_lll = '0;
+
+		s3_lll.a[5:6] = 16'h1234;
+		s3_lll.a[2] = 8'h42;
+
+		s3_lll.a[0] = '1;
+		s3_lll.a[0][1][2:3] = '0;
+
+		s3_lll.b = '1;
+		s3_lll.b[14:15] = '0;
+	end
+
+	always_comb assert(s3_lll==80'hFC00_4200_0012_3400_FFFC);
+
+	struct packed {
+		bit [0:7] [1:0] [0:3] a;
+		bit [0:15] b;		// filler for non-zero offset
+	} s3_lbl;
+
+	initial begin
+		s3_lbl = '0;
+
+		s3_lbl.a[5:6] = 16'h1234;
+		s3_lbl.a[2] = 8'h42;
+
+		s3_lbl.a[0] = '1;
+		s3_lbl.a[0][0][2:3] = '0;
+
+		s3_lbl.b = '1;
+		s3_lbl.b[14:15] = '0;
+	end
+
+	always_comb assert(s3_lbl==80'hFC00_4200_0012_3400_FFFC);
+
+	struct packed {
+		bit [0:7] [0:1] [3:0] a;
+		bit [0:15] b;		// filler for non-zero offset
+	} s3_llb;
+
+	initial begin
+		s3_llb = '0;
+
+		s3_llb.a[5:6] = 16'h1234;
+		s3_llb.a[2] = 8'h42;
+
+		s3_llb.a[0] = '1;
+		s3_llb.a[0][1][1:0] = '0;
+
+		s3_llb.b = '1;
+		s3_llb.b[14:15] = '0;
+	end
+
+	always_comb assert(s3_llb==80'hFC00_4200_0012_3400_FFFC);
+
 `ifndef VERIFIC
 	// Note that the tests below for unpacked arrays in structs rely on the
 	// fact that they are actually packed in Yosys.

tests/various/cellarray_array_connections.ys

@@ -0,0 +1,45 @@
+# Regression test for #3467
+read_verilog <<EOT
+
+module bit_buf (
+    input wire bit_in,
+    output wire bit_out
+);
+    assign bit_out = bit_in;
+endmodule
+
+module top (
+	input wire [3:0] data_in,
+	output wire [3:0] data_out
+);
+
+    wire [3:0] data [0:4];
+
+    assign data[0] = data_in;
+    assign data_out = data[4];
+
+	genvar i;
+	generate
+		for (i=0; i<=3; i=i+1) begin
+			bit_buf bit_buf_instance[3:0] (
+				.bit_in(data[i]),
+				.bit_out(data[i + 1])
+			);
+		end
+	endgenerate
+endmodule
+
+module top2 (
+	input wire [3:0] data_in,
+	output wire [3:0] data_out
+);
+    assign data_out = data_in;
+endmodule
+
+EOT
+
+hierarchy
+proc
+
+miter -equiv -make_assert -flatten top top2 miter
+sat -prove-asserts -verify miter