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Initial synth_ice40 example
Overall structure in place to match the iCE40 flow. Still needs a new example design, and more text for the later sections (which the counter doesn't cover).
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Krystine Sherwin
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2 changed files with 155 additions and 117 deletions
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@ -1,21 +1,17 @@
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Synthesis starter
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-----------------
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..
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Typical phases of a synthesis flow are as follows:
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This page will be a guided walkthrough of the prepackaged iCE40 FPGA synthesis
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script - :cmd:ref:`synth_ice40`. We will take a simple design through each
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step, looking at the commands being called and what they do to the design. While
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:cmd:ref:`synth_ice40` is specific to the iCE40 platform, most of the operations
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we will be discussing are common across the majority of FPGA synthesis scripts.
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Thus, this document will provide a good foundational understanding of how
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synthesis in Yosys is performed, regardless of the actual architecture being
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used.
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- Reading and elaborating the design
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- Higher-level synthesis and optimization
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- Converting ``always``-blocks to logic and registers
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- Perform coarse-grain optimizations (resource sharing, const folding, ...)
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- Handling of memories and other coarse-grain blocks
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- Extracting and optimizing finite state machines
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- Convert remaining logic to bit-level logic functions
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- Perform optimizations on bit-level logic functions
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- Map bit-level logic gates and registers to cell library
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- Write results to output file
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.. seealso:: Advanced usage docs for
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:doc:`/using_yosys/synthesis/synth`
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A simple counter
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~~~~~~~~~~~~~~~~
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@ -23,24 +19,15 @@ A simple counter
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.. role:: yoscrypt(code)
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:language: yoscrypt
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.. TODO:: move current example synth as mapping to cell libraries
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.. TODO:: replace counter.v with a (slightly) more complex design
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which includes hard blocks and maybe an FSM
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replace with a walk through of synth_ice40
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This section covers an `example project`_ available in
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``docs/source/code_examples/intro/``. The project contains a simple ASIC
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synthesis script (``counter.ys``), a digital design written in Verilog
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(``counter.v``), and a simple CMOS cell library (``mycells.lib``).
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.. _example project: https://github.com/YosysHQ/yosys/tree/krys/docs/docs/source/code_examples/intro
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First, let's quickly look at the design:
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First, let's quickly look at the design we'll be synthesizing:
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.. literalinclude:: /code_examples/intro/counter.v
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:language: Verilog
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:caption: ``docs/source/code_examples/intro/counter.v``
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:linenos:
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:name: counter-v
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This is a simple counter with reset and enable. If the reset signal, ``rst``,
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is high then the counter will reset to 0. Otherwise, if the enable signal,
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@ -69,14 +56,40 @@ should see something like the following:
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Storing AST representation for module `$abstract\counter'.
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Successfully finished Verilog frontend.
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.. seealso:: Advanced usage docs for
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:doc:`/using_yosys/more_scripting/load_design`
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Elaboration
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~~~~~~~~~~~
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Now that we are in the interactive shell, we can call Yosys commands directly.
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Let's run :yoscrypt:`hierarchy -check -top counter`. This command declares that
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the top level module is ``counter``, and that we want to expand it and any other
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modules it may use. Any other modules which were loaded are then discarded,
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stopping the following commands from trying to work on them. By passing the
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``-check`` option there we are also telling the :cmd:ref:`hierarchy` command
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that if the design includes any non-blackbox modules without an implementation
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it should return an error.
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Our overall goal is to call :yoscrypt:`synth_ice40 -top counter`, but for now we
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can run each of the commands individually for a better sense of how each part
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contributes to the flow. At the bottom of the :cmd:ref:`help` output for
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:cmd:ref:`synth_ice40` is the complete list of commands called by this script.
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Let's start with the section labeled ``begin``:
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.. literalinclude:: /cmd/synth_ice40.rst
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:language: yoscrypt
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:start-after: begin:
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:end-before: flatten:
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:dedent:
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:caption: ``begin`` section
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:yoscrypt:`read_verilog -D ICE40_HX -lib -specify +/ice40/cells_sim.v` loads the
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iCE40 cell models which allows us to include platform specific IP blocks in our
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design. PLLs are a common example of this, where we might need to reference
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``SB_PLL40_CORE`` directly rather than being able to rely on mapping passes
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later. Since our simple design doesn't use any of these IP blocks, we can safely
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skip this command.
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Let's instead start with run :yoscrypt:`hierarchy -check -top counter`. This
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command declares that the top level module is ``counter``, and that we want to
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expand it and any other modules it may use. Any other modules which were loaded
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are then discarded, preventing the subsequent commands from trying to work on
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them. By passing the ``-check`` option there we are also telling the
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:cmd:ref:`hierarchy` command that if the design includes any non-blackbox
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modules without an implementation it should return an error.
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.. TODO:: more on why :cmd:ref:`hierarchy` is important
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@ -108,27 +121,22 @@ Our circuit now looks like this:
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.. figure:: /_images/code_examples/intro/counter_00.*
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:class: width-helper
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:name: counter-hierarchy
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``counter`` module after :cmd:ref:`hierarchy`
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.. seealso:: Advanced usage docs for :doc:`/using_yosys/more_scripting/load_design`
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Elaboration
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~~~~~~~~~~~
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Notice that block that says "PROC" in :ref:`counter-hierarchy`? Simple
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operations like ``count + 2'd1`` can be extracted from our ``always @`` block in
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:ref:`counter-v`. This gives us the ``$add`` cell we see. But control logic,
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like the ``if .. else``; and memory elements, like the ``count <='2d0``; are not
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so straightforward. To handle these, let us now introduce a new command:
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:ref:`counter-v`. This gives us the ``$add`` cell we see. But control logic
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(like the ``if .. else``) and memory elements (like the ``count <='2d0``) are
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not so straightforward. To handle these, let us now introduce the next command:
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:doc:`/cmd/proc`.
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:cmd:ref:`proc` is a macro command; running a series of other commands which
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work to convert the behavioral logic of processes into multiplexers and
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registers. We go into more detail on :cmd:ref:`proc` later in
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:doc:`/using_yosys/synthesis/proc`, but for now let's see what happens when we
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run it.
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:cmd:ref:`proc` is a macro command like :cmd:ref:`synth_ice40`. Rather than
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processing our design itself, it instead calls a series of other commands. In
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the case of :cmd:ref:`proc`, these sub-commands work to convert the behavioral
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logic of processes into multiplexers and registers. We go into more detail on
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:cmd:ref:`proc` later in :doc:`/using_yosys/synthesis/proc`, but for now let's
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see what happens when we run it.
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.. figure:: /_images/code_examples/intro/counter_proc.*
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:class: width-helper
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@ -136,40 +144,42 @@ run it.
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``counter`` module after :cmd:ref:`proc`
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The ``if`` statements are now modeled with ``$mux`` cells, and the memory
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consists of a ``$dff`` cell. That's getting a bit messy now, so let's chuck in
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a call to :cmd:ref:`opt`.
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consists of a ``$dff`` cell.
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.. figure:: /_images/code_examples/intro/counter_01.*
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:class: width-helper
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.. seealso:: Advanced usage docs for
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:doc:`/using_yosys/synthesis/proc`
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``counter`` module after :cmd:ref:`opt`
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Much better. We can now see that the ``$dff`` and ``$mux`` cells have been
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replaced with a single ``$sdffe``, using the built-in enable and reset ports
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instead.
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.. TODO:: a bit more on :cmd:ref:`opt` here
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Flattening
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~~~~~~~~~~
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At this stage of a synthesis flow there are a few other commands we could run.
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First off is :cmd:ref:`flatten`. If we had any modules within our ``counter``,
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this would replace them with their implementation. Flattening the design like
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this can allow for optimizations between modules which would otherwise be
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missed. Next is :doc:`/cmd/check`.
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missed.
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Depending on the target architecture, we might also run commands such as
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:cmd:ref:`tribuf` with the ``-logic`` option and :cmd:ref:`deminout`. These
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remove tristate and inout constructs respectively, replacing them with logic
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suitable for mapping to an FPGA.
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.. seealso:: Advanced usage docs for :doc:`/using_yosys/synthesis/proc`
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.. literalinclude:: /cmd/synth_ice40.rst
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:language: yoscrypt
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:start-after: flatten:
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:end-before: coarse:
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:dedent:
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:name: flatten
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:caption: ``flatten`` section
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The iCE40 flow puts these commands into thier own :ref:`flatten`,
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while some synthesis scripts will instead include them in the next section.
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The coarse-grain representation
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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At this stage, the design is in coarse-grain representation. It still looks
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recognizable, and cells are word-level operators with parametrizable width.
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There isn't much else we can do for our ``counter`` example, but this is the
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stage of synthesis where we do things like const propagation, expression
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recognizable, and cells are word-level operators with parametrizable width. This
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is the stage of synthesis where we do things like const propagation, expression
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rewriting, and trimming unused parts of wires.
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This is also where we convert our FSMs and hard blocks like DSPs or memories.
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@ -177,59 +187,90 @@ Such elements have to be inferred from patterns in the design and there are
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special passes for each. Detection of these patterns can also be affected by
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optimizations and other transformations done previously.
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In the iCE40 flow we get all the following commands:
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.. literalinclude:: /cmd/synth_ice40.rst
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:language: yoscrypt
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:start-after: coarse:
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:end-before: map_ram:
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:dedent:
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:caption: ``coarse`` section
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.. TODO:: talk more about DSPs (and their associated commands)
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.. TODO:: example_syth ``coarse`` section
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Some of the commands we might use here are:
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- :doc:`/cmd/opt_expr`,
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- :doc:`/cmd/opt_clean`,
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- :doc:`/cmd/check`,
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- :doc:`/cmd/opt`,
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- :doc:`/cmd/fsm`,
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- :doc:`/cmd/memory`,
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- :doc:`/cmd/wreduce`,
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- :doc:`/cmd/peepopt`,
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- :doc:`/cmd/memory`,
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- :doc:`/cmd/pmuxtree`,
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- :doc:`/cmd/alumacc`, and
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- :doc:`/cmd/share`.
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.. seealso:: Advanced usage docs for :doc:`/using_yosys/synthesis/fsm`, and
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:doc:`/using_yosys/synthesis/memory`
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.. seealso:: Advanced usage docs for
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:doc:`/using_yosys/synthesis/fsm`,
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:doc:`/using_yosys/synthesis/memory`, and
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:doc:`/using_yosys/synthesis/opt`
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Logic gate mapping
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~~~~~~~~~~~~~~~~~~
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Hardware mapping
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~~~~~~~~~~~~~~~~
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.. TODO:: example_synth mapping to gates
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.. TODO:: example_synth hardware mapping sections
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:yoscrypt:`techmap` - Map coarse-grain RTL cells (adders, etc.) to fine-grain
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logic gates (AND, OR, NOT, etc.).
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.. literalinclude:: /cmd/synth_ice40.rst
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:language: yoscrypt
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:start-after: map_ram:
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:end-before: map_ffram:
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:dedent:
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:name: map_ram
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:caption: ``map_ram`` section
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When :cmd:ref:`techmap` is used without a map file, it uses a built-in map file
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to map all RTL cell types to a generic library of built-in logic gates and
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registers.
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.. literalinclude:: /cmd/synth_ice40.rst
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:language: yoscrypt
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:start-after: map_ffram:
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:end-before: map_gates:
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:dedent:
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:name: map_ffram
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:caption: ``map_ffram`` section
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The built-in logic gate types are: ``$_NOT_``, ``$_AND_``, ``$_OR_``,
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``$_XOR_``, and ``$_MUX_``.
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.. literalinclude:: /cmd/synth_ice40.rst
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:language: yoscrypt
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:start-after: map_gates:
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:end-before: map_ffs:
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:dedent:
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:name: map_gates
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:caption: ``map_gates`` section
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See :doc:`/yosys_internals/formats/cell_library` for more about the internal
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cells used.
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.. literalinclude:: /cmd/synth_ice40.rst
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:language: yoscrypt
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:start-after: map_ffs:
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:end-before: map_luts:
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:dedent:
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:name: map_ffs
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:caption: ``map_ffs`` section
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.. figure:: /_images/code_examples/intro/counter_02.*
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:class: width-helper
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.. literalinclude:: /cmd/synth_ice40.rst
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:language: yoscrypt
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:start-after: map_luts:
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:end-before: map_cells:
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:dedent:
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:name: map_luts
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:caption: ``map_luts`` section
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``counter`` after :cmd:ref:`techmap`
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Mapping to hardware
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~~~~~~~~~~~~~~~~~~~
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.. TODO:: example_synth mapping to hardware
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:ref:`cmos_lib`
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#. :yoscrypt:`dfflibmap -liberty mycells.lib` - Map registers to available
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hardware flip-flops.
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#. :yoscrypt:`abc -liberty mycells.lib` - Map logic to available hardware gates.
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.. figure:: /_images/code_examples/intro/counter_03.*
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:class: width-helper
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``counter`` after hardware cell mapping
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.. literalinclude:: /cmd/synth_ice40.rst
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:language: yoscrypt
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:start-after: map_cells:
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:end-before: check:
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:dedent:
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:name: map_cells
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:caption: ``map_cells`` section
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:cmd:ref:`dfflibmap`
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This command maps the internal register cell types to the register types
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:cmd:ref:`dfflegalize`
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Specify a set of supported FF cells/cell groups and convert all FFs to them.
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.. seealso:: Advanced usage docs for :doc:`/yosys_internals/techmap`
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.. seealso:: Advanced usage docs for
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:doc:`/yosys_internals/techmap`, and
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:doc:`/using_yosys/synthesis/memory`.
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.. _cmos_lib:
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Final steps
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~~~~~~~~~~~~
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The CMOS cell library
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^^^^^^^^^^^^^^^^^^^^^
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.. TODO:: example_synth final steps (check section and outputting)
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.. literalinclude:: /code_examples/intro/mycells.lib
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:language: Liberty
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:caption: ``docs/source/code_examples/intro/mycells.lib``
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The script file
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~~~~~~~~~~~~~~~
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#. :yoscrypt:`read_verilog -defer counter.v`
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#. :yoscrypt:`clean` - Clean up the design (just the last step of
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:cmd:ref:`opt`).
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#. :yoscrypt:`write_verilog synth.v` - Write final synthesis result to output
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file.
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.. literalinclude:: /code_examples/intro/counter.ys
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.. literalinclude:: /cmd/synth_ice40.rst
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:language: yoscrypt
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:caption: ``docs/source/code_examples/intro/counter.ys``
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:start-after: check:
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:end-before: blif:
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:dedent:
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:name: check
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:caption: ``check`` section
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.. seealso:: Advanced usage docs for :doc:`/using_yosys/synthesis/synth`
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- :doc:`/cmd/check`
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- :doc:`/cmd/autoname`
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- :doc:`/cmd/stat`
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@ -2,6 +2,8 @@
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.. todo:: less academic, check text is coherent
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.. TODO:: can we split some of this into synthesis/techmap ?
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Technology mapping
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==================
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