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Add support for SVA throughout via Verific

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This commit is contained in:
Clifford Wolf 2018-02-21 13:09:47 +01:00
parent 17583b6a21
commit 6d12c83d36
2 changed files with 7 additions and 3 deletions
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19
tests/sva/sva_throughout.sv Normal file
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@ -0,0 +1,19 @@
module top (
input clk,
input a, b, c, d
);
default clocking @(posedge clk); endclocking
assert property (
a |=> b throughout (c ##1 d)
);
`ifndef FAIL
assume property (
a |=> b && c
);
assume property (
b && c |=> b && d
);
`endif
endmodule