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https://github.com/YosysHQ/yosys
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input fanout
This commit is contained in:
Alain Dargelas
parent
d5d58349fd
commit
6cff6d9c49
1 changed files with 100 additions and 25 deletions
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@ -75,6 +75,13 @@ RTLIL::Wire *getParentWire(const RTLIL::SigSpec &sigspec)
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return first_bit.wire;
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}
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std::string getSigSpecName(const RTLIL::SigSpec &sigspec) {
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Wire* wire = getParentWire(sigspec);
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if (wire)
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return wire->name.c_str();
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return "";
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}
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// Find if a signal is used in another (One level)
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bool isSigSpecUsedIn(SigSpec &haystack, SigMap &sigmap, SigSpec &needle)
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{
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@ -204,6 +211,53 @@ SigSpec updateToBuffer(std::map<SigSpec, int> &bufferIndexes,
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return newSig;
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}
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RTLIL::IdString generateSigSpecName(RTLIL::Module *module, const RTLIL::SigSpec &sigspec)
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{
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if (sigspec.empty()) {
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return RTLIL::IdString(); // Empty SigSpec, return empty IdString
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}
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std::stringstream ss;
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if (sigspec.is_wire()) {
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// Handle wires
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ss << sigspec.as_wire()->name.str();
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} else if (sigspec.size() == 1 && sigspec[0].wire) {
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// Handle single-bit SigSpecs
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ss << sigspec[0].wire->name.str();
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if (sigspec[0].wire->width != 1) {
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ss << "[" << sigspec[0].offset << "]";
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}
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} else if (sigspec.is_chunk()) {
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// Handle slices
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RTLIL::Wire *parent_wire = sigspec[0].wire;
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SigChunk chunk = sigspec.as_chunk();
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if (parent_wire) {
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ss << parent_wire->name.str() << "[" << chunk.offset + chunk.width - 1 << ":" << chunk.offset << "]";
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}
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} else if (!sigspec.is_chunk()) {
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// Handle vector of chunks
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int max = 0;
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int min = INT_MAX;
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RTLIL::Wire *parent_wire = sigspec[0].wire;
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for (SigChunk chunk : sigspec.chunks()) {
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max = std::max(max, chunk.offset);
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min = std::min(min, chunk.offset);
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}
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if (parent_wire) {
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ss << parent_wire->name.str() << "[" << max << ":" << min << "]";
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} else {
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ss << "\\sigspec_[" << max << ":" << min << "]";
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}
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} else {
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// Handle other cases (e.g., constants)
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ss << "\\sigspec_";
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}
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RTLIL::IdString base_name = RTLIL::IdString(ss.str());
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return RTLIL::IdString(ss.str());
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}
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// For a given cell with fanout exceeding the limit,
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// - create an array of buffers per cell output chunk (2 dimentions array of buffers)
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// - connect cell chunk to corresponding buffers
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@ -212,17 +266,21 @@ SigSpec updateToBuffer(std::map<SigSpec, int> &bufferIndexes,
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// The capacity of the buffers might be larger than the limit in a given pass,
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// Recursion is used until all buffers capacity is under or at the limit.
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void fixfanout(RTLIL::Design *design, RTLIL::Module *module, SigMap &sigmap, dict<RTLIL::SigSpec, std::set<Cell *>> &sig2CellsInFanout,
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RTLIL::Cell *cell, int fanout, int limit, bool debug)
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SigSpec sigToBuffer, int fanout, int limit, bool debug)
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{
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if (sigToBuffer.is_fully_const()) {
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return;
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}
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std::string signame = generateSigSpecName(module, sigToBuffer).c_str();
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if (fanout <= limit) {
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if (debug) {
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std::cout << "Nothing to do for: " << cell->name.c_str() << std::endl;
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std::cout << "Nothing to do for: " << signame << std::endl;
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std::cout << "Fanout: " << fanout << std::endl;
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}
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return; // No need to insert buffers
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} else {
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if (debug) {
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std::cout << "Something to do for: " << cell->name.c_str() << std::endl;
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std::cout << "Something to do for: " << signame << std::endl;
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std::cout << "Fanout: " << fanout << std::endl;
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}
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}
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@ -235,14 +293,11 @@ void fixfanout(RTLIL::Design *design, RTLIL::Module *module, SigMap &sigmap, dic
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if (debug) {
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std::cout << "Fanout: " << fanout << "\n";
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std::cout << "Limit: " << limit << "\n";
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std::cout << "Mum_buffers: " << num_buffers << "\n";
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std::cout << "Num_buffers: " << num_buffers << "\n";
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std::cout << "Max_output_per_buffer: " << max_output_per_buffer << "\n";
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std::cout << "CELL: " << cell->name.c_str() << "\n" << std::flush;
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std::cout << "Signal: " << signame << "\n" << std::flush;
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}
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// Get cell output
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RTLIL::SigSpec cellOutSig = getCellOutputSigSpec(cell, sigmap);
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// Keep track of the fanout count for each new buffer
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std::map<Cell *, int> bufferActualFanout;
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// Array of buffers (The buffer output signal and the buffer cell) per cell output chunks
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@ -251,25 +306,28 @@ void fixfanout(RTLIL::Design *design, RTLIL::Module *module, SigMap &sigmap, dic
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std::map<SigSpec, int> bufferIndexes;
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// Create new buffers and new wires
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for (SigChunk chunk : cellOutSig.chunks()) {
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int index_buffer = 0;
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for (SigChunk chunk : sigToBuffer.chunks()) {
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std::vector<std::tuple<RTLIL::SigSpec, Cell *>> buffer_chunk_outputs;
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for (int i = 0; i < num_buffers; ++i) {
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RTLIL::Cell *buffer = module->addCell(NEW_ID2_SUFFIX("fbuf"), ID($pos));
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std::cout << "Name: " << signame + "_fbuf" + std::to_string(index_buffer) << std::endl;
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RTLIL::Cell *buffer = module->addCell(signame + "_fbuf" + std::to_string(index_buffer), ID($pos));
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bufferActualFanout[buffer] = 0;
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RTLIL::SigSpec buffer_output = module->addWire(NEW_ID2_SUFFIX("fbuf"), chunk.size());
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RTLIL::SigSpec buffer_output = module->addWire(signame + "_wbuf" + std::to_string(index_buffer) , chunk.size());
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buffer->setPort(ID(A), chunk);
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buffer->setPort(ID(Y), sigmap(buffer_output));
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buffer->fixup_parameters();
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buffer_chunk_outputs.push_back(std::make_tuple(buffer_output, buffer)); // Old - New
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bufferIndexes[chunk] = 0;
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index_buffer++;
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}
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buffer_outputs.emplace(sigmap(SigSpec(chunk)), buffer_chunk_outputs);
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}
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// Cumulate all cells in the fanout of this cell
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std::set<Cell *> fanoutcells = sig2CellsInFanout[cellOutSig];
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for (int i = 0; i < cellOutSig.size(); i++) {
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SigSpec bit_sig = cellOutSig.extract(i, 1);
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std::set<Cell *> fanoutcells = sig2CellsInFanout[sigToBuffer];
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for (int i = 0; i < sigToBuffer.size(); i++) {
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SigSpec bit_sig = sigToBuffer.extract(i, 1);
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for (Cell *c : sig2CellsInFanout[sigmap(bit_sig)]) {
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fanoutcells.insert(c);
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}
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@ -288,6 +346,7 @@ void fixfanout(RTLIL::Design *design, RTLIL::Module *module, SigMap &sigmap, dic
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if (debug)
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std::cout << " IS A CHUNK" << std::endl;
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if (buffer_outputs.find(actual) != buffer_outputs.end()) {
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if (debug) std::cout << " MATCH" << std::endl;
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// Input is one of the cell's outputs, its a match
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SigSpec newSig = updateToBuffer(bufferIndexes, buffer_outputs, sig2CellsInFanout, bufferActualFanout,
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max_output_per_buffer, fanoutcell, actual, debug);
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@ -298,11 +357,12 @@ void fixfanout(RTLIL::Design *design, RTLIL::Module *module, SigMap &sigmap, dic
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// Input of that cell is a list of chunks
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if (debug)
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std::cout << " NOT A CHUNK" << std::endl;
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if (isSigSpecUsedIn(actual, sigmap, cellOutSig)) {
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if (isSigSpecUsedIn(actual, sigmap, sigToBuffer)) {
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// Create a new chunk vector
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std::vector<RTLIL::SigChunk> newChunks;
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for (SigChunk chunk : actual.chunks()) {
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if (buffer_outputs.find(chunk) != buffer_outputs.end()) {
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if (debug) std::cout << " MATCH" << std::endl;
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SigSpec newSig =
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updateToBuffer(bufferIndexes, buffer_outputs, sig2CellsInFanout, bufferActualFanout,
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max_output_per_buffer, fanoutcell, chunk, debug);
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@ -329,7 +389,8 @@ void fixfanout(RTLIL::Design *design, RTLIL::Module *module, SigMap &sigmap, dic
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removeBuffer(module, sigmap, fanoutcells, itr->first, debug);
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} else {
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// Recursively fix the fanout of the newly created buffers
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fixfanout(design, module, sigmap, sig2CellsInFanout, itr->first, itr->second, limit, debug);
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RTLIL::SigSpec sig = getCellOutputSigSpec(itr->first, sigmap);
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fixfanout(design, module, sigmap, sig2CellsInFanout, sig, itr->second, limit, debug);
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}
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}
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}
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@ -402,7 +463,7 @@ std::string substringuntil(const std::string &str, char delimiter)
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}
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}
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void splitNet(Design *design, std::set<std::string> &netsToSplitS, RTLIL::SigSpec &sigToSplit, bool formalFriendly, bool inputsToo = false)
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void splitNet(Design *design, std::set<std::string> &netsToSplitS, RTLIL::SigSpec &sigToSplit, bool formalFriendly, bool inputPort = false)
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{
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Wire *parentWire = getParentWire(sigToSplit);
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if (!parentWire)
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@ -416,17 +477,14 @@ void splitNet(Design *design, std::set<std::string> &netsToSplitS, RTLIL::SigSpe
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netsToSplitS.insert(parent);
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// Splitnets has to be invoke with individual nets. Sending a bunch of nets as selection,
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// selects more than required (bug in selection/splitnets).
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std::cout << "splitnets -ports_only w:" << parent << std::endl;
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Pass::call(design, "splitnets w:" + parent); // Wire
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if (!formalFriendly) {
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// Formal verification does not like ports to be split.
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// This option will prevent some buffering to happen on high fanout input/output ports,
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// but it will make formal happy.
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if (inputsToo) {
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std::cout << "splitnets -ports_only x:" << parent << std::endl;
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Pass::call(design, "splitnets -ports_only x:" + parent); // Input/Output port
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if (inputPort) {
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Pass::call(design, "splitnets -ports_only i:" + parent); // Input port
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} else {
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std::cout << "splitnets -ports_only o:" << parent << std::endl;
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Pass::call(design, "splitnets -ports_only o:" + parent); // Output port
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}
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}
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@ -496,7 +554,7 @@ struct AnnotateCellFanout : public ScriptPass {
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calculateFanout(module, sigmap, sig2CellsInFanout, cellFanout, sigFanout);
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std::set<std::string> netsToSplitS;
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// Split output nets of cells with high fanout
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// Split cells' output nets with high fanout
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for (auto itrCell : cellFanout) {
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Cell *cell = itrCell.first;
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int fanout = itrCell.second;
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@ -512,7 +570,6 @@ struct AnnotateCellFanout : public ScriptPass {
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if (wire->port_input) {
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SigSpec inp = sigmap(wire);
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int fanout = sigFanout[inp];
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std::cout << "Input" << wire->name.c_str() << " fanout: " << fanout << std::endl;
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if (limit > 0 && (fanout > limit)) {
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wiresToSplit.insert(wire);
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}
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@ -532,17 +589,35 @@ struct AnnotateCellFanout : public ScriptPass {
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dict<RTLIL::SigSpec, std::set<Cell *>> sig2CellsInFanout;
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calculateFanout(module, sigmap, sig2CellsInFanout, cellFanout, sigFanout);
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// Fix cells outputs with high fanout
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for (auto itrCell : cellFanout) {
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Cell *cell = itrCell.first;
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int fanout = itrCell.second;
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if (limit > 0 && (fanout > limit)) {
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fixfanout(design, module, sigmap, sig2CellsInFanout, cell, fanout, limit, debug);
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RTLIL::SigSpec cellOutSig = getCellOutputSigSpec(cell, sigmap);
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fixfanout(design, module, sigmap, sig2CellsInFanout, cellOutSig, fanout, limit, debug);
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fixedFanout = true;
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} else {
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// Add attribute with fanout info to every cell
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cell->set_string_attribute("$FANOUT", std::to_string(fanout));
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}
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}
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// Fix module input nets with high fanout
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std::map<SigSpec, int> sigsToFix;
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for (Wire *wire : module->wires()) {
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if (wire->port_input) {
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SigSpec inp = sigmap(wire);
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int fanout = sigFanout[inp];
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if (limit > 0 && (fanout > limit)) {
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sigsToFix.emplace(inp, fanout);
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}
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}
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}
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for (auto sig : sigsToFix) {
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fixfanout(design, module, sigmap, sig2CellsInFanout, sig.first, sig.second, limit, debug);
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fixedFanout = true;
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}
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}
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if (fixedFanout) {
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