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Fixed trailing whitespaces

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This commit is contained in:
Clifford Wolf 2015-07-02 11:14:30 +02:00
parent 053058d781
commit 6c84341f22
195 changed files with 729 additions and 729 deletions
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2
tests/fsm/generate.py
View file

@ -108,4 +108,4 @@ for idx in range(50):
print('cd ..')
print('miter -equiv -flatten -ignore_gold_x -make_outputs -make_outcmp gold gate miter')
print('sat -verify-no-timeout -timeout 20 -seq 5 -set-at 1 %s_rst 1 -prove trigger 0 -prove-skip 1 -show-inputs -show-outputs miter' % ('gold' if rst2 else 'in'))

4
tests/realmath/generate.py
View file

@ -39,7 +39,7 @@ def random_expression(depth = 3, maxparam = 0):
return op + '(' + recursion() + ', ' + recursion() + ')'
raise
for idx in range(100):
for idx in range(100):
with open('temp/uut_%05d.v' % idx, 'w') as f:
with redirect_stdout(f):
print('module uut_%05d(output [63:0] %s);\n' % (idx, ', '.join(['y%02d' % i for i in range(100)])))
@ -91,4 +91,4 @@ for idx in range(100):
print(' compare_ref_syn(%2d, r%02d, s%02d);' % (i, i, i))
print('end')
print('endmodule')

2
tests/share/generate.py
View file

@ -72,4 +72,4 @@ for idx in range(100):
print('tee -a temp/all_share_log.txt share -aggressive gate')
print('miter -equiv -flatten -ignore_gold_x -make_outputs -make_outcmp gold gate miter')
print('sat -set-def-inputs -verify -prove trigger 0 -show-inputs -show-outputs miter')

6
tests/simple/loops.v
View file

@ -41,10 +41,10 @@ begin
keysched_last_key_i = key_i;
else
keysched_last_key_i = keysched_new_key_o;
if (round == 0 && addroundkey_start_i)
begin
data_var = addroundkey_data_i;
data_var = addroundkey_data_i;
round_key_var = key_i;
round_data_var = round_key_var ^ data_var;
next_addroundkey_data_reg = round_data_var;
@ -66,7 +66,7 @@ begin
end
else if (addroundkey_round == round && keysched_ready_o)
begin
data_var = addroundkey_data_i;
data_var = addroundkey_data_i;
round_key_var = keysched_new_key_o;
round_data_var = round_key_var ^ data_var;
next_addroundkey_data_reg = round_data_var;

2
tests/simple/mem2reg.v
View file

@ -47,7 +47,7 @@ endmodule
// http://www.reddit.com/r/yosys/comments/28d9lx/problem_with_concatenation_of_two_dimensional/
module mem2reg_test3( input clk, input [8:0] din_a, output reg [7:0] dout_a, output [7:0] dout_b);
reg [7:0] dint_c [0:7];
reg [7:0] dint_c [0:7];
always @(posedge clk)
begin
{dout_a[0], dint_c[3]} <= din_a;

4
tests/simple/omsp_dbg_uart.v
View file

@ -22,13 +22,13 @@ always @(uart_state or mem_burst)
RX_DATA : uart_state_nxt = RX_SYNC;
default : uart_state_nxt = RX_CMD;
endcase
always @(posedge dbg_clk or posedge dbg_rst)
if (dbg_rst) uart_state <= RX_SYNC;
else if (xfer_done | mem_burst) uart_state <= uart_state_nxt;
assign cmd_valid = (uart_state==RX_CMD) & xfer_done;
assign xfer_done = uart_state!=RX_SYNC;
endmodule