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https://github.com/YosysHQ/yosys
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Fixed trailing whitespaces
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053058d781
commit
6c84341f22
195 changed files with 729 additions and 729 deletions
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@ -2,11 +2,11 @@
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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@ -97,7 +97,7 @@ void simplemap_reduce(RTLIL::Module *module, RTLIL::Cell *cell)
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if (sig_y.size() == 0)
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return;
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if (sig_a.size() == 0) {
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if (cell->type == "$reduce_and") module->connect(RTLIL::SigSig(sig_y, RTLIL::SigSpec(1, sig_y.size())));
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if (cell->type == "$reduce_or") module->connect(RTLIL::SigSig(sig_y, RTLIL::SigSpec(0, sig_y.size())));
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@ -197,7 +197,7 @@ void simplemap_lognot(RTLIL::Module *module, RTLIL::Cell *cell)
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if (sig_y.size() == 0)
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return;
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if (sig_y.size() > 1) {
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module->connect(RTLIL::SigSig(sig_y.extract(1, sig_y.size()-1), RTLIL::SigSpec(0, sig_y.size()-1)));
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sig_y = sig_y.extract(0, 1);
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@ -221,7 +221,7 @@ void simplemap_logbin(RTLIL::Module *module, RTLIL::Cell *cell)
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if (sig_y.size() == 0)
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return;
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if (sig_y.size() > 1) {
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module->connect(RTLIL::SigSig(sig_y.extract(1, sig_y.size()-1), RTLIL::SigSpec(0, sig_y.size()-1)));
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sig_y = sig_y.extract(0, 1);
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@ -549,5 +549,5 @@ struct SimplemapPass : public Pass {
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}
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}
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} SimplemapPass;
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PRIVATE_NAMESPACE_END
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