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Fixed trailing whitespaces

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This commit is contained in:
Clifford Wolf 2015-07-02 11:14:30 +02:00
parent 053058d781
commit 6c84341f22
195 changed files with 729 additions and 729 deletions
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8
passes/techmap/aigmap.cc
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@ -2,11 +2,11 @@
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
*
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
@ -108,7 +108,7 @@ struct AigmapPass : public Pass {
if (node.inverter)
bit = module->NotGate(NEW_ID, bit);
skip_inverter:
for (auto &op : node.outports)
module->connect(cell->getPort(op.first)[op.second], bit);
@ -145,5 +145,5 @@ struct AigmapPass : public Pass {
}
}
} AigmapPass;
PRIVATE_NAMESPACE_END