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Fixed trailing whitespaces
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parent
053058d781
commit
6c84341f22
195 changed files with 729 additions and 729 deletions
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@ -2,11 +2,11 @@
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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@ -159,7 +159,7 @@ void rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool verbos
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for (auto &it2 : cell->connections())
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connected_signals.add(it2.second);
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}
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SigMap assign_map(module);
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pool<RTLIL::SigSpec> direct_sigs;
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pool<RTLIL::Wire*> direct_wires;
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@ -368,7 +368,7 @@ struct OptCleanPass : public Pass {
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log_pop();
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}
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} OptCleanPass;
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struct CleanPass : public Pass {
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CleanPass() : Pass("clean", "remove unused cells and wires") { }
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virtual void help()
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@ -432,5 +432,5 @@ struct CleanPass : public Pass {
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ct_all.clear();
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}
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} CleanPass;
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PRIVATE_NAMESPACE_END
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