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https://github.com/YosysHQ/yosys
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Fixed trailing whitespaces
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parent
053058d781
commit
6c84341f22
195 changed files with 729 additions and 729 deletions
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@ -2,11 +2,11 @@
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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@ -145,5 +145,5 @@ struct FsmPass : public Pass {
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log_pop();
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}
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} FsmPass;
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PRIVATE_NAMESPACE_END
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@ -2,11 +2,11 @@
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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@ -191,5 +191,5 @@ struct FsmDetectPass : public Pass {
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muxtree_cells.clear();
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}
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} FsmDetectPass;
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PRIVATE_NAMESPACE_END
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@ -2,11 +2,11 @@
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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@ -275,5 +275,5 @@ struct FsmExpandPass : public Pass {
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}
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}
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} FsmExpandPass;
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PRIVATE_NAMESPACE_END
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@ -3,11 +3,11 @@
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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* Copyright (C) 2012 Martin Schmölzer <martin@schmoelzer.at>
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*
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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@ -2,11 +2,11 @@
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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@ -241,7 +241,7 @@ static void extract_fsm(RTLIL::Wire *wire)
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{
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log("Extracting FSM `%s' from module `%s'.\n", wire->name.c_str(), module->name.c_str());
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// get input and output signals for state ff
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// get input and output signals for state ff
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RTLIL::SigSpec dff_out = assign_map(RTLIL::SigSpec(wire));
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RTLIL::SigSpec dff_in(RTLIL::State::Sm, wire->width);
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@ -460,5 +460,5 @@ struct FsmExtractPass : public Pass {
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sig2trigger.clear();
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}
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} FsmExtractPass;
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PRIVATE_NAMESPACE_END
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@ -2,11 +2,11 @@
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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@ -58,5 +58,5 @@ struct FsmInfoPass : public Pass {
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}
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}
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} FsmInfoPass;
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PRIVATE_NAMESPACE_END
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@ -2,11 +2,11 @@
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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@ -350,5 +350,5 @@ struct FsmMapPass : public Pass {
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}
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}
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} FsmMapPass;
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PRIVATE_NAMESPACE_END
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@ -2,11 +2,11 @@
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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@ -75,14 +75,14 @@ struct FsmOpt
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fsm_data.reset_state = old_to_new_state.at(fsm_data.reset_state);
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}
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}
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bool signal_is_unused(RTLIL::SigSpec sig)
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{
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RTLIL::SigBit bit = sig.to_single_sigbit();
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if (bit.wire == NULL || bit.wire->attributes.count("\\unused_bits") == 0)
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return false;
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char *str = strdup(bit.wire->attributes["\\unused_bits"].decode_string().c_str());
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for (char *tok = strtok(str, " "); tok != NULL; tok = strtok(NULL, " ")) {
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if (tok[0] && bit.offset == atoi(tok)) {
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@ -347,5 +347,5 @@ struct FsmOptPass : public Pass {
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}
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}
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} FsmOptPass;
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PRIVATE_NAMESPACE_END
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@ -2,11 +2,11 @@
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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@ -93,7 +93,7 @@ static void fsm_recode(RTLIL::Cell *cell, RTLIL::Module *module, FILE *fm_set_fs
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fsm_data.state_bits = new_num_state_bits;
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} else
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log_error("FSM encoding `%s' is not supported!\n", encoding.c_str());
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if (encfile)
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fprintf(encfile, ".fsm %s %s\n", log_id(module), RTLIL::unescape_id(cell->parameters["\\NAME"].decode_string()).c_str());
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@ -134,7 +134,7 @@ struct FsmRecodePass : public Pass {
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log("\n");
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log("This pass reassign the state encodings for FSM cells. At the moment only\n");
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log("one-hot encoding and binary encoding is supported.\n");
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log(" -encoding <type>\n");
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log(" specify the encoding scheme used for FSMs without the\n");
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log(" 'fsm_encoding' attribute or with the attribute set to `auto'.\n");
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@ -193,5 +193,5 @@ struct FsmRecodePass : public Pass {
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fclose(encfile);
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}
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} FsmRecodePass;
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PRIVATE_NAMESPACE_END
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@ -2,11 +2,11 @@
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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