3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-08-31 07:14:55 +00:00

Fixed trailing whitespaces

This commit is contained in:
Clifford Wolf 2015-07-02 11:14:30 +02:00
parent 053058d781
commit 6c84341f22
195 changed files with 729 additions and 729 deletions

View file

@ -22,7 +22,7 @@
\item Convert remaining logic to bit-level logic functions
\item Perform optimizations on bit-level logic functions
\item Map bit-level logic gates and registers to cell library
\item Write results to output file
\item Write results to output file
\end{itemize}
\end{frame}