mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-08-24 20:16:01 +00:00
Code Activity

Fixed trailing whitespaces

Browse source
This commit is contained in:
Clifford Wolf 2015-07-02 11:14:30 +02:00
parent 053058d781
commit 6c84341f22
195 changed files with 729 additions and 729 deletions
Download patch file Download diff file Expand all files Collapse all files

6
manual/PRESENTATION_ExAdv/sym_mul_map.v
View file

@ -4,12 +4,12 @@ module \$mul (A, B, Y);
parameter A_WIDTH = 1;
parameter B_WIDTH = 1;
parameter Y_WIDTH = 1;
input [A_WIDTH-1:0] A;
input [B_WIDTH-1:0] B;
output [Y_WIDTH-1:0] Y;
wire _TECHMAP_FAIL_ = A_WIDTH != B_WIDTH || B_WIDTH != Y_WIDTH;
MYMUL #( .WIDTH(Y_WIDTH) ) g ( .A(A), .B(B), .Y(Y) );
endmodule