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Fixed trailing whitespaces

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Clifford Wolf 2015-07-02 11:14:30 +02:00
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6
manual/APPNOTE_010_Verilog_to_BLIF.tex
View file

@ -150,11 +150,11 @@ write_blif softusb_navre.blif
\end{figure}
The first and last line obviously read the Verilog file and write the BLIF
file.
file.
\medskip
The 2nd line checks the design hierarchy and instantiates parametrized
The 2nd line checks the design hierarchy and instantiates parametrized
versions of the modules in the design, if necessary. In the case of this
simple design this is a no-op. However, as a general rule a synthesis script
should always contain this command as first command after reading the input
@ -174,7 +174,7 @@ instead of {\tt opt}.
\item The command {\tt proc} converts {\it processes} (Yosys' internal
representation of Verilog {\tt always}- and {\tt initial}-blocks) to circuits
of multiplexers and storage elements (various types of flip-flops).
\item The command {\tt memory} converts Yosys' internal representations of
\item The command {\tt memory} converts Yosys' internal representations of
arrays and array accesses to multi-port block memories, and then maps this
block memories to address decoders and flip-flops, unless the option {\tt -nomap}
is used, in which case the multi-port block memories stay in the design

40
manual/APPNOTE_011_Design_Investigation.tex
View file

@ -256,7 +256,7 @@ Verilog file containing blackbox modules. There are two ways to load cell
descriptions into Yosys: First the Verilog file for the cell library can be
passed directly to the {\tt show} command using the {\tt -lib <filename>}
option. Secondly it is possible to load cell libraries into the design with
the {\tt read\_verilog -lib <filename>} command. The 2nd method has the great
the {\tt read\_verilog -lib <filename>} command. The 2nd method has the great
advantage that the library only needs to be loaded once and can then be used
in all subsequent calls to the {\tt show} command.
@ -296,7 +296,7 @@ In addition to {\it what\/} to display one also needs to carefully decide
{\it when\/} to display it, with respect to the synthesis flow. In general
it is a good idea to troubleshoot a circuit in the earliest state in which
a problem can be reproduced. So if, for example, the internal state before calling
the {\tt techmap} command already fails to verify, it is better to troubleshoot
the {\tt techmap} command already fails to verify, it is better to troubleshoot
the coarse-grain version of the circuit before {\tt techmap} than the gate-level
circuit after {\tt techmap}.
@ -316,7 +316,7 @@ yosys> ls
1 modules:
example
yosys> cd example
yosys> cd example
yosys [example]> ls
@ -708,7 +708,7 @@ For example (see Fig.~\ref{submod} for the circuit diagram of {\tt selstage}):
{\scriptsize
\begin{verbatim}
yosys [selstage]> eval -set s2,s1 4'b1001 -set d 4'hc -show n2 -show n1
9. Executing EVAL pass (evaluate the circuit given an input).
Full command line: eval -set s2,s1 4'b1001 -set d 4'hc -show n2 -show n1
Eval result: \n2 = 2'10.
@ -729,10 +729,10 @@ The {\tt -table} option can be used to create a truth table. For example:
{\scriptsize
\begin{verbatim}
yosys [selstage]> eval -set-undef -set d[3:1] 0 -table s1,d[0]
10. Executing EVAL pass (evaluate the circuit given an input).
Full command line: eval -set-undef -set d[3:1] 0 -table s1,d[0]
\s1 \d [0] | \n1 \n2
---- ------ | ---- ----
2'00 1'0 | 2'00 2'00
@ -743,7 +743,7 @@ The {\tt -table} option can be used to create a truth table. For example:
2'10 1'1 | 2'xx 2'10
2'11 1'0 | 2'00 2'00
2'11 1'1 | 2'xx 2'11
Assumend undef (x) value for the following singals: \s2
\end{verbatim}
}
@ -780,11 +780,11 @@ Final proof equation: \ok = 1'1
Solving problem with 2790 variables and 8241 clauses..
SAT proof finished - model found: FAIL!
______ ___ ___ _ _ _ _
______ ___ ___ _ _ _ _
(_____ \ / __) / __) (_) | | | |
_____) )___ ___ ___ _| |__ _| |__ _____ _| | _____ __| | |
| ____/ ___) _ \ / _ (_ __) (_ __|____ | | || ___ |/ _ |_|
| | | | | |_| | |_| || | | | / ___ | | || ____( (_| |_
| | | | | |_| | |_| || | | | / ___ | | || ____( (_| |_
|_| |_| \___/ \___/ |_| |_| \_____|_|\_)_____)\____|_|
@ -811,15 +811,15 @@ Final proof equation: \ok = 1'1
Solving problem with 2790 variables and 8257 clauses..
SAT proof finished - no model found: SUCCESS!
/$$$$$$ /$$$$$$$$ /$$$$$$$
/$$__ $$ | $$_____/ | $$__ $$
| $$ \ $$ | $$ | $$ \ $$
| $$ | $$ | $$$$$ | $$ | $$
| $$ | $$ | $$__/ | $$ | $$
| $$/$$ $$ | $$ | $$ | $$
/$$$$$$ /$$$$$$$$ /$$$$$$$
/$$__ $$ | $$_____/ | $$__ $$
| $$ \ $$ | $$ | $$ \ $$
| $$ | $$ | $$$$$ | $$ | $$
| $$ | $$ | $$__/ | $$ | $$
| $$/$$ $$ | $$ | $$ | $$
| $$$$$$/ /$$| $$$$$$$$ /$$| $$$$$$$//$$
\____ $$$|__/|________/|__/|_______/|__/
\__/
\__/
\end{lstlisting}
\caption{Experiments with the miter circuit from Fig.~\ref{primetest}. The first attempt of proving that 31
is prime failed because the SAT solver found a creative way of factorizing 31 using integer overflow.}
@ -840,20 +840,20 @@ corresponding input values. For Example:
{\scriptsize
\begin{verbatim}
yosys [selstage]> sat -show s1,s2,d -set s1 s2 -set n2,n1 4'b1001
11. Executing SAT pass (solving SAT problems in the circuit).
Full command line: sat -show s1,s2,d -set s1 s2 -set n2,n1 4'b1001
Setting up SAT problem:
Import set-constraint: \s1 = \s2
Import set-constraint: { \n2 \n1 } = 4'1001
Final constraint equation: { \n2 \n1 \s1 } = { 4'1001 \s2 }
Imported 3 cells to SAT database.
Import show expression: { \s1 \s2 \d }
Solving problem with 81 variables and 207 clauses..
SAT solving finished - model found:
Signal Name Dec Hex Bin
-------------------- ---------- ---------- ---------------
\d 9 9 1001

26
manual/APPNOTE_012_Verilog_to_BTOR.tex
View file

@ -182,7 +182,7 @@ file:
\begin{figure}[H]
\begin{lstlisting}[language=sh,numbers=none]
$ boolector fsm.btor
$ boolector fsm.btor
unsat
\end{lstlisting}
\renewcommand{\figurename}{Listing}
@ -204,16 +204,16 @@ executed by {\tt verilog2btor.sh}.
\begin{figure}[H]
\begin{lstlisting}[language=sh]
read_verilog -sv $1;
hierarchy -top $3; hierarchy -libdir $DIR;
hierarchy -check;
proc; opt;
read_verilog -sv $1;
hierarchy -top $3; hierarchy -libdir $DIR;
hierarchy -check;
proc; opt;
opt_const -mux_undef; opt;
rename -hide;;;
splice; opt;
memory_dff -wr_only; memory_collect;;
flatten;;
memory_unpack;
memory_unpack;
splitnets -driver;
setundef -zero -undriven;
opt;;;
@ -242,7 +242,7 @@ line:
collecting the memories to multi-port memories.
\item Flattening the design to get only one module.
\item Separating read and write memories.
\item Splitting the signals that are partially assigned
\item Splitting the signals that are partially assigned
\item Setting undef to zero value.
\item Final optimization pass.
\item Writing BTOR file.
@ -259,10 +259,10 @@ modified Yosys script file:
\begin{figure}[H]
\begin{lstlisting}[language=sh,numbers=none]
read_verilog -sv $1;
hierarchy -top $3; hierarchy -libdir $DIR;
hierarchy -check;
proc; opt;
read_verilog -sv $1;
hierarchy -top $3; hierarchy -libdir $DIR;
hierarchy -check;
proc; opt;
opt_const -mux_undef; opt;
rename -hide;;;
splice; opt;
@ -294,7 +294,7 @@ module array(input clk);
mem[counter] <= counter;
end
assert property (!(counter > 8'd0) ||
assert property (!(counter > 8'd0) ||
mem[counter - 8'd1] == counter - 8'd1);
endmodule
@ -422,7 +422,7 @@ Robert Brummayer and Armin Biere and Florian Lonsing, BTOR:
Bit-Precise Modelling of Word-Level Problems for Model Checking\\
\url{http://fmv.jku.at/papers/BrummayerBiereLonsing-BPR08.pdf}
\bibitem{nuxmv}
\bibitem{nuxmv}
Roberto Cavada and Alessandro Cimatti and Michele Dorigatti and
Alberto Griggio and Alessandro Mariotti and Andrea Micheli and Sergio
Mover and Marco Roveri and Stefano Tonetta, The nuXmv Symbolic Model

2
manual/CHAPTER_Appnotes.tex
View file

@ -5,7 +5,7 @@
% \begin{fixme}
% This appendix will cover some typical use-cases of Yosys in the form of application notes.
% \end{fixme}
%
%
% \section{Synthesizing using a Cell Library in Liberty Format}
% \section{Reverse Engeneering the MOS6502 from an NMOS Transistor Netlist}
% \section{Reconfigurable Coarse-Grain Synthesis using Intersynth}

8
manual/CHAPTER_Basics.tex
View file

@ -56,8 +56,8 @@ and how they relate to different kinds of synthesis.
Regardless of the way a lower level representation of a circuit is
obtained (synthesis or manual design), the lower level representation is usually
verified by comparing simulation results of the lower level and the higher level
representation \footnote{In recent years formal equivalence
checking also became an important verification method for validating RTL and
representation \footnote{In recent years formal equivalence
checking also became an important verification method for validating RTL and
lower abstraction representation of the design.}.
Therefore even if no synthesis is used, there must still be a simulatable
representation of the circuit in all levels to allow for verification of the
@ -270,7 +270,7 @@ signals.
\subsection{Expressions in Verilog}
In all situations where Verilog accepts a constant value or signal name,
In all situations where Verilog accepts a constant value or signal name,
expressions using arithmetic operations such as
\lstinline[language=Verilog]{+}, \lstinline[language=Verilog]{-} and \lstinline[language=Verilog]{*},
boolean operations such as
@ -470,7 +470,7 @@ optimizes the design. First of all because not all optimizations are applicable
designs and all synthesis tasks. Some optimizations work (best) on a coarse-grained level
(with complex cells such as adders or multipliers) and others work (best) on a fine-grained
level (single bit gates). Some optimizations target area and others target speed.
Some work well on large designs while others don't scale well and can only be applied
Some work well on large designs while others don't scale well and can only be applied
to small designs.
A good tool is capable of applying a wide range of optimizations at different

2
manual/CHAPTER_Eval/grep-it.sh
View file

@ -79,6 +79,6 @@ done
# if [ $luts -gt 0 -a $luts_ys -gt 0 ]; then luts_p=$(( 100*luts_ys / luts )); else luts_p=NaN; fi
# if [ $freq -gt 0 -a $freq_ys -gt 0 ]; then freq_p=$(( 100*freq_ys / freq )); else freq_p=NaN; fi
# printf '%-30s %3s %3s %3s\n' $mod $regs_p $luts_p $freq_p
#
#
# done

6
manual/CHAPTER_Intro.tex
View file

@ -35,7 +35,7 @@ The proposed custom HDL synthesis tool should be licensed under a Free
and Open Source Software (FOSS) licence. So an existing FOSS Verilog or VHDL
synthesis tool would have been needed as basis to build upon. The main advantages
of choosing Verilog or VHDL is the ability to synthesize existing HDL code and
to mitigate the requirement for circuit-designers to learn a new language. In order to take full advantage of any existing FOSS Verilog or VHDL tool,
to mitigate the requirement for circuit-designers to learn a new language. In order to take full advantage of any existing FOSS Verilog or VHDL tool,
such a tool would have to provide a feature-complete implementation of the
synthesizable HDL subset.
@ -68,7 +68,7 @@ problem of implementing a HDL synthesis tool is approached in the case of
Yosys.
Chapter~\ref{chapter:overview} contains a more detailed overview of the
implementation of Yosys. This chapter covers the data structures used in
implementation of Yosys. This chapter covers the data structures used in
Yosys to represent a design in detail and is therefore recommended reading
for everyone who is interested in understanding the Yosys internals.
@ -81,7 +81,7 @@ is recommended reading for everyone who actually wants to read or write
Yosys source code. The chapter concludes with an example loadable module
for Yosys.
Chapters~\ref{chapter:verilog}, \ref{chapter:opt}, and \ref{chapter:techmap}
Chapters~\ref{chapter:verilog}, \ref{chapter:opt}, and \ref{chapter:techmap}
cover three important pieces of the synthesis pipeline: The Verilog frontend,
the optimization passes and the technology mapping to the target architecture,
respectively.

2
manual/CHAPTER_Optimize.tex
View file

@ -241,7 +241,7 @@ by identifying the driver for the state signal.
From there the {\tt \$mux}-tree driving the state register inputs is
recursively traversed. All select inputs are control signals and the leaves of the
{\tt \$mux}-tree are the states. The algorithm fails if a non-constant leaf
{\tt \$mux}-tree are the states. The algorithm fails if a non-constant leaf
that is not the state signal itself is found.
The list of control outputs is initialized with the bits from the state signal.

10
manual/CHAPTER_Overview.tex
View file

@ -307,11 +307,11 @@ process $proc$ff_with_en_and_async_reset.v:4$1
switch \reset
case 1'1
assign $0\q[0:0] 1'0
case
case
switch \enable
case 1'1
assign $0\q[0:0] \d
case
case
end
end
sync posedge \clock
@ -338,7 +338,7 @@ An RTLIL::CaseRule is a container for zero or more assignments (RTLIL::SigSig)
and zero or more RTLIL::SwitchRule objects. An RTLIL::SwitchRule objects is a
container for zero or more RTLIL::CaseRule objects.
In the above example the lines $2 \dots 12$ are the root case. Here {\tt \$0\textbackslash{}q[0:0]} is first
In the above example the lines $2 \dots 12$ are the root case. Here {\tt \$0\textbackslash{}q[0:0]} is first
assigned the old value {\tt \textbackslash{}q} as default value (line 2). The root case
also contains an RTLIL::SwitchRule object (lines $3 \dots 12$). Such an object is very similar to the C {\tt switch}
statement as it uses a control signal ({\tt \textbackslash{}reset} in this case) to determine
@ -371,7 +371,7 @@ process $proc$ff_with_en_and_async_reset.v:4$1
switch \enable
case 1'1
assign $0\q[0:0] \d
case
case
end
sync posedge \clock
update \q $0\q[0:0]
@ -449,7 +449,7 @@ See Sec.~\ref{sec:memcells} for details about the memory cell types.
Yosys reads and processes commands from synthesis scripts, command line arguments and
an interactive command prompt. Yosys commands consist of a command name and an optional
whitespace separated list of arguments. Commands are terminated using the newline character
or a semicolon ({\tt ;}). Empty lines and lines starting with the hash sign ({\tt \#}) are ignored.
or a semicolon ({\tt ;}). Empty lines and lines starting with the hash sign ({\tt \#}) are ignored.
See Sec.~\ref{sec:typusecase} for an example synthesis script.
The command {\tt help} can be used to access the command reference manual.

2
manual/CHAPTER_Prog/stubnets.cc
View file

@ -1,5 +1,5 @@
// This is free and unencumbered software released into the public domain.
//
//
// Anyone is free to copy, modify, publish, use, compile, sell, or
// distribute this software, either in source code form or as a compiled
// binary, for any purpose, commercial or non-commercial, and by any

204
manual/CHAPTER_StateOfTheArt/simlib_hana.v
View file

@ -1,4 +1,4 @@
/*
/*
Copyright (C) 2009-2010 Parvez Ahmad
Written by Parvez Ahmad <parvez_ahmad@yahoo.co.uk>.
@ -45,7 +45,7 @@ module AND3 #(parameter SIZE = 3) (input [SIZE-1:0] in, output out);
assign out = &in;
endmodule
module AND4 #(parameter SIZE = 4) (input [SIZE-1:0] in, output out);
assign out = &in;
@ -63,7 +63,7 @@ module OR3 #(parameter SIZE = 3) (input [SIZE-1:0] in, output out);
assign out = |in;
endmodule
module OR4 #(parameter SIZE = 4) (input [SIZE-1:0] in, output out);
assign out = |in;
@ -82,7 +82,7 @@ module NAND3 #(parameter SIZE = 3) (input [SIZE-1:0] in, output out);
assign out = ~&in;
endmodule
module NAND4 #(parameter SIZE = 4) (input [SIZE-1:0] in, output out);
assign out = ~&in;
@ -100,7 +100,7 @@ module NOR3 #(parameter SIZE = 3) (input [SIZE-1:0] in, output out);
assign out = ~|in;
endmodule
module NOR4 #(parameter SIZE = 4) (input [SIZE-1:0] in, output out);
assign out = ~|in;
@ -119,7 +119,7 @@ module XOR3 #(parameter SIZE = 3) (input [SIZE-1:0] in, output out);
assign out = ^in;
endmodule
module XOR4 #(parameter SIZE = 4) (input [SIZE-1:0] in, output out);
assign out = ^in;
@ -138,7 +138,7 @@ module XNOR3 #(parameter SIZE = 3) (input [SIZE-1:0] in, output out);
assign out = ~^in;
endmodule
module XNOR4 #(parameter SIZE = 4) (input [SIZE-1:0] in, output out);
assign out = ~^in;
@ -156,7 +156,7 @@ always @(in or enable)
1'b1 : out = 2'b10;
endcase
end
endmodule
endmodule
module DEC2 (input [1:0] in, input enable, output reg [3:0] out);
@ -171,7 +171,7 @@ always @(in or enable)
2'b11 : out = 4'b1000;
endcase
end
endmodule
endmodule
module DEC3 (input [2:0] in, input enable, output reg [7:0] out);
@ -190,7 +190,7 @@ always @(in or enable)
3'b111 : out = 8'b10000000;
endcase
end
endmodule
endmodule
module DEC4 (input [3:0] in, input enable, output reg [15:0] out);
@ -217,7 +217,7 @@ always @(in or enable)
4'b1111 : out = 16'b1000000000000000;
endcase
end
endmodule
endmodule
module DEC5 (input [4:0] in, input enable, output reg [31:0] out);
always @(in or enable)
@ -259,7 +259,7 @@ always @(in or enable)
5'b11111 : out = 32'b10000000000000000000000000000000;
endcase
end
endmodule
endmodule
module DEC6 (input [5:0] in, input enable, output reg [63:0] out);
@ -335,7 +335,7 @@ always @(in or enable)
6'b111111 : out = 64'b1000000000000000000000000000000000000000000000000000000000000000;
endcase
end
endmodule
endmodule
module MUX2(input [1:0] in, input select, output reg out);
@ -345,7 +345,7 @@ always @( in or select)
0: out = in[0];
1: out = in[1];
endcase
endmodule
endmodule
module MUX4(input [3:0] in, input [1:0] select, output reg out);
@ -357,7 +357,7 @@ always @( in or select)
2: out = in[2];
3: out = in[3];
endcase
endmodule
endmodule
module MUX8(input [7:0] in, input [2:0] select, output reg out);
@ -373,7 +373,7 @@ always @( in or select)
6: out = in[6];
7: out = in[7];
endcase
endmodule
endmodule
module MUX16(input [15:0] in, input [3:0] select, output reg out);
@ -396,7 +396,7 @@ always @( in or select)
14: out = in[14];
15: out = in[15];
endcase
endmodule
endmodule
module MUX32(input [31:0] in, input [4:0] select, output reg out);
@ -435,7 +435,7 @@ always @( in or select)
30: out = in[30];
31: out = in[31];
endcase
endmodule
endmodule
module MUX64(input [63:0] in, input [5:0] select, output reg out);
@ -506,7 +506,7 @@ always @( in or select)
62: out = in[62];
63: out = in[63];
endcase
endmodule
endmodule
module ADD1(input in1, in2, cin, output out, cout);
@ -514,41 +514,41 @@ assign {cout, out} = in1 + in2 + cin;
endmodule
module ADD2 #(parameter SIZE = 2)(input [SIZE-1:0] in1, in2,
module ADD2 #(parameter SIZE = 2)(input [SIZE-1:0] in1, in2,
input cin, output [SIZE-1:0] out, output cout);
assign {cout, out} = in1 + in2 + cin;
endmodule
module ADD4 #(parameter SIZE = 4)(input [SIZE-1:0] in1, in2,
module ADD4 #(parameter SIZE = 4)(input [SIZE-1:0] in1, in2,
input cin, output [SIZE-1:0] out, output cout);
assign {cout, out} = in1 + in2 + cin;
endmodule
module ADD8 #(parameter SIZE = 8)(input [SIZE-1:0] in1, in2,
module ADD8 #(parameter SIZE = 8)(input [SIZE-1:0] in1, in2,
input cin, output [SIZE-1:0] out, output cout);
assign {cout, out} = in1 + in2 + cin;
endmodule
module ADD16 #(parameter SIZE = 16)(input [SIZE-1:0] in1, in2,
module ADD16 #(parameter SIZE = 16)(input [SIZE-1:0] in1, in2,
input cin, output [SIZE-1:0] out, output cout);
assign {cout, out} = in1 + in2 + cin;
endmodule
module ADD32 #(parameter SIZE = 32)(input [SIZE-1:0] in1, in2,
module ADD32 #(parameter SIZE = 32)(input [SIZE-1:0] in1, in2,
input cin, output [SIZE-1:0] out, output cout);
assign {cout, out} = in1 + in2 + cin;
endmodule
module ADD64 #(parameter SIZE = 64)(input [SIZE-1:0] in1, in2,
module ADD64 #(parameter SIZE = 64)(input [SIZE-1:0] in1, in2,
input cin, output [SIZE-1:0] out, output cout);
assign {cout, out} = in1 + in2 + cin;
@ -561,41 +561,41 @@ assign {cout, out} = in1 - in2 - cin;
endmodule
module SUB2 #(parameter SIZE = 2)(input [SIZE-1:0] in1, in2,
module SUB2 #(parameter SIZE = 2)(input [SIZE-1:0] in1, in2,
input cin, output [SIZE-1:0] out, output cout);
assign {cout, out} = in1 - in2 - cin;
endmodule
module SUB4 #(parameter SIZE = 4)(input [SIZE-1:0] in1, in2,
module SUB4 #(parameter SIZE = 4)(input [SIZE-1:0] in1, in2,
input cin, output [SIZE-1:0] out, output cout);
assign {cout, out} = in1 - in2 - cin;
endmodule
module SUB8 #(parameter SIZE = 8)(input [SIZE-1:0] in1, in2,
module SUB8 #(parameter SIZE = 8)(input [SIZE-1:0] in1, in2,
input cin, output [SIZE-1:0] out, output cout);
assign {cout, out} = in1 - in2 - cin;
endmodule
module SUB16 #(parameter SIZE = 16)(input [SIZE-1:0] in1, in2,
module SUB16 #(parameter SIZE = 16)(input [SIZE-1:0] in1, in2,
input cin, output [SIZE-1:0] out, output cout);
assign {cout, out} = in1 - in2 - cin;
endmodule
module SUB32 #(parameter SIZE = 32)(input [SIZE-1:0] in1, in2,
module SUB32 #(parameter SIZE = 32)(input [SIZE-1:0] in1, in2,
input cin, output [SIZE-1:0] out, output cout);
assign {cout, out} = in1 - in2 - cin;
endmodule
module SUB64 #(parameter SIZE = 64)(input [SIZE-1:0] in1, in2,
module SUB64 #(parameter SIZE = 64)(input [SIZE-1:0] in1, in2,
input cin, output [SIZE-1:0] out, output cout);
assign {cout, out} = in1 - in2 - cin;
@ -651,7 +651,7 @@ assign rem = in1%in2;
endmodule
module DIV2 #(parameter SIZE = 2)(input [SIZE-1:0] in1, in2,
module DIV2 #(parameter SIZE = 2)(input [SIZE-1:0] in1, in2,
output [SIZE-1:0] out, rem);
assign out = in1/in2;
@ -659,7 +659,7 @@ assign rem = in1%in2;
endmodule
module DIV4 #(parameter SIZE = 4)(input [SIZE-1:0] in1, in2,
module DIV4 #(parameter SIZE = 4)(input [SIZE-1:0] in1, in2,
output [SIZE-1:0] out, rem);
assign out = in1/in2;
@ -667,7 +667,7 @@ assign rem = in1%in2;
endmodule
module DIV8 #(parameter SIZE = 8)(input [SIZE-1:0] in1, in2,
module DIV8 #(parameter SIZE = 8)(input [SIZE-1:0] in1, in2,
output [SIZE-1:0] out, rem);
assign out = in1/in2;
@ -675,7 +675,7 @@ assign rem = in1%in2;
endmodule
module DIV16 #(parameter SIZE = 16)(input [SIZE-1:0] in1, in2,
module DIV16 #(parameter SIZE = 16)(input [SIZE-1:0] in1, in2,
output [SIZE-1:0] out, rem);
assign out = in1/in2;
@ -683,7 +683,7 @@ assign rem = in1%in2;
endmodule
module DIV32 #(parameter SIZE = 32)(input [SIZE-1:0] in1, in2,
module DIV32 #(parameter SIZE = 32)(input [SIZE-1:0] in1, in2,
output [SIZE-1:0] out, rem);
assign out = in1/in2;
@ -691,7 +691,7 @@ assign rem = in1%in2;
endmodule
module DIV64 #(parameter SIZE = 64)(input [SIZE-1:0] in1, in2,
module DIV64 #(parameter SIZE = 64)(input [SIZE-1:0] in1, in2,
output [SIZE-1:0] out, rem);
assign out = in1/in2;
@ -711,7 +711,7 @@ always @(posedge clk or posedge reset)
q <= 0;
else
q <= d;
endmodule
endmodule
module SFF(input d, clk, set, output reg q);
always @(posedge clk or posedge set)
@ -719,7 +719,7 @@ always @(posedge clk or posedge set)
q <= 1;
else
q <= d;
endmodule
endmodule
module RSFF(input d, clk, set, reset, output reg q);
always @(posedge clk or posedge reset or posedge set)
@ -745,30 +745,30 @@ module LATCH(input d, enable, output reg q);
always @( d or enable)
if(enable)
q <= d;
endmodule
endmodule
module RLATCH(input d, reset, enable, output reg q);
always @( d or enable or reset)
if(enable)
if(reset)
q <= 0;
else
else
q <= d;
endmodule
endmodule
module LSHIFT1 #(parameter SIZE = 1)(input in, shift, val, output reg out);
always @ (in, shift, val) begin
if(shift)
out = val;
else
else
out = in;
end
endmodule
module LSHIFT2 #(parameter SIZE = 2)(input [SIZE-1:0] in,
module LSHIFT2 #(parameter SIZE = 2)(input [SIZE-1:0] in,
input [SIZE-1:0] shift, input val,
output reg [SIZE-1:0] out);
@ -776,58 +776,58 @@ always @(in or shift or val) begin
out = in << shift;
if(val)
out = out | ({SIZE-1 {1'b1} } >> (SIZE-1-shift));
end
end
endmodule
module LSHIFT4 #(parameter SIZE = 4)(input [SIZE-1:0] in,
module LSHIFT4 #(parameter SIZE = 4)(input [SIZE-1:0] in,
input [2:0] shift, input val, output reg [SIZE-1:0] out);
always @(in or shift or val) begin
out = in << shift;
if(val)
out = out | ({SIZE-1 {1'b1} } >> (SIZE-1-shift));
end
end
endmodule
module LSHIFT8 #(parameter SIZE = 8)(input [SIZE-1:0] in,
module LSHIFT8 #(parameter SIZE = 8)(input [SIZE-1:0] in,
input [3:0] shift, input val, output reg [SIZE-1:0] out);
always @(in or shift or val) begin
out = in << shift;
if(val)
out = out | ({SIZE-1 {1'b1} } >> (SIZE-1-shift));
end
end
endmodule
module LSHIFT16 #(parameter SIZE = 16)(input [SIZE-1:0] in,
module LSHIFT16 #(parameter SIZE = 16)(input [SIZE-1:0] in,
input [4:0] shift, input val, output reg [SIZE-1:0] out);
always @(in or shift or val) begin
out = in << shift;
if(val)
out = out | ({SIZE-1 {1'b1} } >> (SIZE-1-shift));
end
end
endmodule
module LSHIFT32 #(parameter SIZE = 32)(input [SIZE-1:0] in,
module LSHIFT32 #(parameter SIZE = 32)(input [SIZE-1:0] in,
input [5:0] shift, input val, output reg [SIZE-1:0] out);
always @(in or shift or val) begin
out = in << shift;
if(val)
out = out | ({SIZE-1 {1'b1} } >> (SIZE-1-shift));
end
end
endmodule
module LSHIFT64 #(parameter SIZE = 64)(input [SIZE-1:0] in,
module LSHIFT64 #(parameter SIZE = 64)(input [SIZE-1:0] in,
input [6:0] shift, input val, output reg [SIZE-1:0] out);
always @(in or shift or val) begin
out = in << shift;
if(val)
out = out | ({SIZE-1 {1'b1} } >> (SIZE-1-shift));
end
end
endmodule
module RSHIFT1 #(parameter SIZE = 1)(input in, shift, val, output reg out);
@ -841,7 +841,7 @@ end
endmodule
module RSHIFT2 #(parameter SIZE = 2)(input [SIZE-1:0] in,
module RSHIFT2 #(parameter SIZE = 2)(input [SIZE-1:0] in,
input [SIZE-1:0] shift, input val,
output reg [SIZE-1:0] out);
@ -849,12 +849,12 @@ always @(in or shift or val) begin
out = in >> shift;
if(val)
out = out | ({SIZE-1 {1'b1} } << (SIZE-1-shift));
end
end
endmodule
module RSHIFT4 #(parameter SIZE = 4)(input [SIZE-1:0] in,
module RSHIFT4 #(parameter SIZE = 4)(input [SIZE-1:0] in,
input [2:0] shift, input val,
output reg [SIZE-1:0] out);
@ -862,10 +862,10 @@ always @(in or shift or val) begin
out = in >> shift;
if(val)
out = out | ({SIZE-1 {1'b1} } << (SIZE-1-shift));
end
end
endmodule
module RSHIFT8 #(parameter SIZE = 8)(input [SIZE-1:0] in,
module RSHIFT8 #(parameter SIZE = 8)(input [SIZE-1:0] in,
input [3:0] shift, input val,
output reg [SIZE-1:0] out);
@ -873,11 +873,11 @@ always @(in or shift or val) begin
out = in >> shift;
if(val)
out = out | ({SIZE-1 {1'b1} } << (SIZE-1-shift));
end
end
endmodule
module RSHIFT16 #(parameter SIZE = 16)(input [SIZE-1:0] in,
module RSHIFT16 #(parameter SIZE = 16)(input [SIZE-1:0] in,
input [4:0] shift, input val,
output reg [SIZE-1:0] out);
@ -885,11 +885,11 @@ always @(in or shift or val) begin
out = in >> shift;
if(val)
out = out | ({SIZE-1 {1'b1} } << (SIZE-1-shift));
end
end
endmodule
module RSHIFT32 #(parameter SIZE = 32)(input [SIZE-1:0] in,
module RSHIFT32 #(parameter SIZE = 32)(input [SIZE-1:0] in,
input [5:0] shift, input val,
output reg [SIZE-1:0] out);
@ -897,10 +897,10 @@ always @(in or shift or val) begin
out = in >> shift;
if(val)
out = out | ({SIZE-1 {1'b1} } << (SIZE-1-shift));
end
end
endmodule
module RSHIFT64 #(parameter SIZE = 64)(input [SIZE-1:0] in,
module RSHIFT64 #(parameter SIZE = 64)(input [SIZE-1:0] in,
input [6:0] shift, input val,
output reg [SIZE-1:0] out);
@ -908,10 +908,10 @@ always @(in or shift or val) begin
out = in >> shift;
if(val)
out = out | ({SIZE-1 {1'b1} } << (SIZE-1-shift));
end
end
endmodule
module CMP1 #(parameter SIZE = 1) (input in1, in2,
module CMP1 #(parameter SIZE = 1) (input in1, in2,
output reg equal, unequal, greater, lesser);
always @ (in1 or in2) begin
@ -920,7 +920,7 @@ always @ (in1 or in2) begin
unequal = 0;
greater = 0;
lesser = 0;
end
end
else begin
equal = 0;
unequal = 1;
@ -928,17 +928,17 @@ always @ (in1 or in2) begin
if(in1 < in2) begin
greater = 0;
lesser = 1;
end
end
else begin
greater = 1;
lesser = 0;
end
end
end
end
end
endmodule
module CMP2 #(parameter SIZE = 2) (input [SIZE-1:0] in1, in2,
module CMP2 #(parameter SIZE = 2) (input [SIZE-1:0] in1, in2,
output reg equal, unequal, greater, lesser);
always @ (in1 or in2) begin
@ -947,7 +947,7 @@ always @ (in1 or in2) begin
unequal = 0;
greater = 0;
lesser = 0;
end
end
else begin
equal = 0;
unequal = 1;
@ -955,16 +955,16 @@ always @ (in1 or in2) begin
if(in1 < in2) begin
greater = 0;
lesser = 1;
end
end
else begin
greater = 1;
lesser = 0;
end
end
end
end
end
endmodule
module CMP4 #(parameter SIZE = 4) (input [SIZE-1:0] in1, in2,
module CMP4 #(parameter SIZE = 4) (input [SIZE-1:0] in1, in2,
output reg equal, unequal, greater, lesser);
always @ (in1 or in2) begin
@ -973,7 +973,7 @@ always @ (in1 or in2) begin
unequal = 0;
greater = 0;
lesser = 0;
end
end
else begin
equal = 0;
unequal = 1;
@ -981,16 +981,16 @@ always @ (in1 or in2) begin
if(in1 < in2) begin
greater = 0;
lesser = 1;
end
end
else begin
greater = 1;
lesser = 0;
end
end
end
end
end
endmodule
module CMP8 #(parameter SIZE = 8) (input [SIZE-1:0] in1, in2,
module CMP8 #(parameter SIZE = 8) (input [SIZE-1:0] in1, in2,
output reg equal, unequal, greater, lesser);
always @ (in1 or in2) begin
@ -999,7 +999,7 @@ always @ (in1 or in2) begin
unequal = 0;
greater = 0;
lesser = 0;
end
end
else begin
equal = 0;
unequal = 1;
@ -1007,16 +1007,16 @@ always @ (in1 or in2) begin
if(in1 < in2) begin
greater = 0;
lesser = 1;
end
end
else begin
greater = 1;
lesser = 0;
end
end
end
end
end
endmodule
module CMP16 #(parameter SIZE = 16) (input [SIZE-1:0] in1, in2,
module CMP16 #(parameter SIZE = 16) (input [SIZE-1:0] in1, in2,
output reg equal, unequal, greater, lesser);
always @ (in1 or in2) begin
@ -1025,7 +1025,7 @@ always @ (in1 or in2) begin
unequal = 0;
greater = 0;
lesser = 0;
end
end
else begin
equal = 0;
unequal = 1;
@ -1033,16 +1033,16 @@ always @ (in1 or in2) begin
if(in1 < in2) begin
greater = 0;
lesser = 1;
end
end
else begin
greater = 1;
lesser = 0;
end
end
end
end
end
endmodule
module CMP32 #(parameter SIZE = 32) (input [SIZE-1:0] in1, in2,
module CMP32 #(parameter SIZE = 32) (input [SIZE-1:0] in1, in2,
output reg equal, unequal, greater, lesser);
always @ (in1 or in2) begin
@ -1051,7 +1051,7 @@ always @ (in1 or in2) begin
unequal = 0;
greater = 0;
lesser = 0;
end
end
else begin
equal = 0;
unequal = 1;
@ -1059,16 +1059,16 @@ always @ (in1 or in2) begin
if(in1 < in2) begin
greater = 0;
lesser = 1;
end
end
else begin
greater = 1;
lesser = 0;
end
end
end
end
end
endmodule
module CMP64 #(parameter SIZE = 64) (input [SIZE-1:0] in1, in2,
module CMP64 #(parameter SIZE = 64) (input [SIZE-1:0] in1, in2,
output reg equal, unequal, greater, lesser);
always @ (in1 or in2) begin
@ -1077,7 +1077,7 @@ always @ (in1 or in2) begin
unequal = 0;
greater = 0;
lesser = 0;
end
end
else begin
equal = 0;
unequal = 1;
@ -1085,12 +1085,12 @@ always @ (in1 or in2) begin
if(in1 < in2) begin
greater = 0;
lesser = 1;
end
end
else begin
greater = 1;
lesser = 0;
end
end
end
end
end
endmodule

4
manual/CHAPTER_StateOfTheArt/simlib_yosys.v
View file

@ -2,11 +2,11 @@
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
*
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR

8
manual/CHAPTER_Verilog.tex
View file

@ -550,23 +550,23 @@ process $proc$<input>:1$1
switch \in2
case 1'1
assign $1\out1[0:0] $logic_not$<input>:4$2_Y
case
case
assign $1\out1[0:0] \in1
end
switch \in3
case 1'1
assign $0\out2[0:0] \out2
case
case
end
switch \in4
case 1'1
switch \in5
case 1'1
assign $0\out3[0:0] \in6
case
case
assign $0\out3[0:0] \in7
end
case
case
end
sync posedge \clock
update \out1 $0\out1[0:0]

6
manual/PRESENTATION_ExAdv.tex
View file

@ -844,13 +844,13 @@ module adff2dff (CLK, ARST, D, Q);
parameter CLK_POLARITY = 1;
parameter ARST_POLARITY = 1;
parameter ARST_VALUE = 0;
input CLK, ARST;
input [WIDTH-1:0] D;
output reg [WIDTH-1:0] Q;
wire [1023:0] _TECHMAP_DO_ = "proc";
wire _TECHMAP_FAIL_ = !CLK_POLARITY || !ARST_POLARITY;
\end{lstlisting}
\vss}

8
manual/PRESENTATION_ExAdv/addshift_map.v
View file

@ -4,17 +4,17 @@ module \$add (A, B, Y);
parameter A_WIDTH = 1;
parameter B_WIDTH = 1;
parameter Y_WIDTH = 1;
input [A_WIDTH-1:0] A;
input [B_WIDTH-1:0] B;
output [Y_WIDTH-1:0] Y;
parameter _TECHMAP_BITS_CONNMAP_ = 0;
parameter _TECHMAP_CONNMAP_A_ = 0;
parameter _TECHMAP_CONNMAP_B_ = 0;
wire _TECHMAP_FAIL_ = A_WIDTH != B_WIDTH || B_WIDTH < Y_WIDTH ||
_TECHMAP_CONNMAP_A_ != _TECHMAP_CONNMAP_B_;
assign Y = A << 1;
endmodule

6
manual/PRESENTATION_ExAdv/red_or3x1_map.v
View file

@ -3,10 +3,10 @@ module \$reduce_or (A, Y);
parameter A_SIGNED = 0;
parameter A_WIDTH = 0;
parameter Y_WIDTH = 0;
input [A_WIDTH-1:0] A;
output [Y_WIDTH-1:0] Y;
function integer min;
input integer a, b;
begin
@ -16,7 +16,7 @@ module \$reduce_or (A, Y);
min = b;
end
endfunction
genvar i;
generate begin
if (A_WIDTH == 0) begin

6
manual/PRESENTATION_ExAdv/sym_mul_map.v
View file

@ -4,12 +4,12 @@ module \$mul (A, B, Y);
parameter A_WIDTH = 1;
parameter B_WIDTH = 1;
parameter Y_WIDTH = 1;
input [A_WIDTH-1:0] A;
input [B_WIDTH-1:0] B;
output [Y_WIDTH-1:0] Y;
wire _TECHMAP_FAIL_ = A_WIDTH != B_WIDTH || B_WIDTH != Y_WIDTH;
MYMUL #( .WIDTH(Y_WIDTH) ) g ( .A(A), .B(B), .Y(Y) );
endmodule

4
manual/PRESENTATION_ExOth.tex
View file

@ -33,7 +33,7 @@ as {\tt \%ci} and {\tt \%co}, can be used to figure out how parts of the design
are connected.
\item
Commands such as {\tt submod}, {\tt expose}, {\tt splice}, \dots can be used
Commands such as {\tt submod}, {\tt expose}, {\tt splice}, \dots can be used
to transform the design into an equivialent design that is easier to analyse.
\item
@ -115,7 +115,7 @@ The {\tt sat} command in Yosys can be used to perform Symbolic Model Checking.
\end{frame}
\begin{frame}[t]{Example: Formal Equivalence Checking (1/2)}
Remember the following example?
Remember the following example?
\vskip1em
\vbox to 0cm{

2
manual/PRESENTATION_ExSyn.tex
View file

@ -22,7 +22,7 @@
\item Convert remaining logic to bit-level logic functions
\item Perform optimizations on bit-level logic functions
\item Map bit-level logic gates and registers to cell library
\item Write results to output file
\item Write results to output file
\end{itemize}
\end{frame}

2
manual/PRESENTATION_Intro/counter.ys
View file

@ -1,4 +1,4 @@
# read design
# read design
read_verilog counter.v
hierarchy -check -top counter

2
manual/PRESENTATION_Prog.tex
View file

@ -325,7 +325,7 @@ Simulation models (i.e. {\it documentation\/} :-) for the internal cell library:
\bigskip
The lower-case cell types (such as {\tt \$and}) are parameterized cells of variable
width. This so-called {\it RTL Cells\/} are the cells described in {\tt simlib.v}.
width. This so-called {\it RTL Cells\/} are the cells described in {\tt simlib.v}.
\bigskip
The upper-case cell types (such as {\tt \$\_AND\_}) are single-bit cells that are not

2
manual/command-reference-manual.tex
View file

@ -2988,7 +2988,7 @@ from non-zero to zero in the test design.
Write the current design to an SPICE netlist file.
-big_endian
generate multi-bit ports in MSB first order
generate multi-bit ports in MSB first order
(default is LSB first)
-neg net_name