mirror of
				https://github.com/YosysHQ/yosys
				synced 2025-10-31 03:32:29 +00:00 
			
		
		
		
	Encode filename unprintable chars
This commit is contained in:
		
							parent
							
								
									2b1aeb44d9
								
							
						
					
					
						commit
						6c65ca4e50
					
				
					 4 changed files with 42 additions and 27 deletions
				
			
		|  | @ -1240,7 +1240,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, | |||
| 
 | ||||
| 				// create the indirection wire
 | ||||
| 				std::stringstream sstr; | ||||
| 				sstr << "$indirect$" << ref->name.c_str() << "$" << filename << ":" << location.first_line << "$" << (autoidx++); | ||||
| 				sstr << "$indirect$" << ref->name.c_str() << "$" << RTLIL::encode_filename(filename) << ":" << location.first_line << "$" << (autoidx++); | ||||
| 				std::string tmp_str = sstr.str(); | ||||
| 				add_wire_for_ref(ref, tmp_str); | ||||
| 
 | ||||
|  | @ -2127,7 +2127,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, | |||
| 			std::swap(data_range_left, data_range_right); | ||||
| 
 | ||||
| 		std::stringstream sstr; | ||||
| 		sstr << "$mem2bits$" << str << "$" << filename << ":" << location.first_line << "$" << (autoidx++); | ||||
| 		sstr << "$mem2bits$" << str << "$" << RTLIL::encode_filename(filename) << ":" << location.first_line << "$" << (autoidx++); | ||||
| 		std::string wire_id = sstr.str(); | ||||
| 
 | ||||
| 		AstNode *wire = new AstNode(AST_WIRE, new AstNode(AST_RANGE, mkconst_int(data_range_left, true), mkconst_int(data_range_right, true))); | ||||
|  | @ -2714,14 +2714,14 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, | |||
| 			// mask and shift operations, disabled for now
 | ||||
| 
 | ||||
| 			AstNode *wire_mask = new AstNode(AST_WIRE, new AstNode(AST_RANGE, mkconst_int(source_width-1, true), mkconst_int(0, true))); | ||||
| 			wire_mask->str = stringf("$bitselwrite$mask$%s:%d$%d", filename.c_str(), location.first_line, autoidx++); | ||||
| 			wire_mask->str = stringf("$bitselwrite$mask$%s:%d$%d", RTLIL::encode_filename(filename).c_str(), location.first_line, autoidx++); | ||||
| 			wire_mask->attributes[ID::nosync] = AstNode::mkconst_int(1, false); | ||||
| 			wire_mask->is_logic = true; | ||||
| 			while (wire_mask->simplify(true, false, false, 1, -1, false, false)) { } | ||||
| 			current_ast_mod->children.push_back(wire_mask); | ||||
| 
 | ||||
| 			AstNode *wire_data = new AstNode(AST_WIRE, new AstNode(AST_RANGE, mkconst_int(source_width-1, true), mkconst_int(0, true))); | ||||
| 			wire_data->str = stringf("$bitselwrite$data$%s:%d$%d", filename.c_str(), location.first_line, autoidx++); | ||||
| 			wire_data->str = stringf("$bitselwrite$data$%s:%d$%d", RTLIL::encode_filename(filename).c_str(), location.first_line, autoidx++); | ||||
| 			wire_data->attributes[ID::nosync] = AstNode::mkconst_int(1, false); | ||||
| 			wire_data->is_logic = true; | ||||
| 			while (wire_data->simplify(true, false, false, 1, -1, false, false)) { } | ||||
|  | @ -2732,7 +2732,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, | |||
| 			shift_expr->detectSignWidth(shamt_width_hint, shamt_sign_hint); | ||||
| 
 | ||||
| 			AstNode *wire_sel = new AstNode(AST_WIRE, new AstNode(AST_RANGE, mkconst_int(shamt_width_hint-1, true), mkconst_int(0, true))); | ||||
| 			wire_sel->str = stringf("$bitselwrite$sel$%s:%d$%d", filename.c_str(), location.first_line, autoidx++); | ||||
| 			wire_sel->str = stringf("$bitselwrite$sel$%s:%d$%d", RTLIL::encode_filename(filename).c_str(), location.first_line, autoidx++); | ||||
| 			wire_sel->attributes[ID::nosync] = AstNode::mkconst_int(1, false); | ||||
| 			wire_sel->is_logic = true; | ||||
| 			wire_sel->is_signed = shamt_sign_hint; | ||||
|  | @ -2809,7 +2809,7 @@ skip_dynamic_range_lvalue_expansion:; | |||
| 	if (stage > 1 && (type == AST_ASSERT || type == AST_ASSUME || type == AST_LIVE || type == AST_FAIR || type == AST_COVER) && current_block != NULL) | ||||
| 	{ | ||||
| 		std::stringstream sstr; | ||||
| 		sstr << "$formal$" << filename << ":" << location.first_line << "$" << (autoidx++); | ||||
| 		sstr << "$formal$" << RTLIL::encode_filename(filename) << ":" << location.first_line << "$" << (autoidx++); | ||||
| 		std::string id_check = sstr.str() + "_CHECK", id_en = sstr.str() + "_EN"; | ||||
| 
 | ||||
| 		AstNode *wire_check = new AstNode(AST_WIRE); | ||||
|  | @ -2918,7 +2918,7 @@ skip_dynamic_range_lvalue_expansion:; | |||
| 			newNode = new AstNode(AST_BLOCK); | ||||
| 
 | ||||
| 			AstNode *wire_tmp = new AstNode(AST_WIRE, new AstNode(AST_RANGE, mkconst_int(width_hint-1, true), mkconst_int(0, true))); | ||||
| 			wire_tmp->str = stringf("$splitcmplxassign$%s:%d$%d", filename.c_str(), location.first_line, autoidx++); | ||||
| 			wire_tmp->str = stringf("$splitcmplxassign$%s:%d$%d", RTLIL::encode_filename(filename).c_str(), location.first_line, autoidx++); | ||||
| 			current_ast_mod->children.push_back(wire_tmp); | ||||
| 			current_scope[wire_tmp->str] = wire_tmp; | ||||
| 			wire_tmp->attributes[ID::nosync] = AstNode::mkconst_int(1, false); | ||||
|  | @ -2956,7 +2956,7 @@ skip_dynamic_range_lvalue_expansion:; | |||
| 			(children[0]->children.size() == 1 || children[0]->children.size() == 2) && children[0]->children[0]->type == AST_RANGE) | ||||
| 	{ | ||||
| 		std::stringstream sstr; | ||||
| 		sstr << "$memwr$" << children[0]->str << "$" << filename << ":" << location.first_line << "$" << (autoidx++); | ||||
| 		sstr << "$memwr$" << children[0]->str << "$" << RTLIL::encode_filename(filename) << ":" << location.first_line << "$" << (autoidx++); | ||||
| 		std::string id_addr = sstr.str() + "_ADDR", id_data = sstr.str() + "_DATA", id_en = sstr.str() + "_EN"; | ||||
| 
 | ||||
| 		int mem_width, mem_size, addr_bits; | ||||
|  | @ -3228,7 +3228,7 @@ skip_dynamic_range_lvalue_expansion:; | |||
| 					AstNode *reg = new AstNode(AST_WIRE, new AstNode(AST_RANGE, | ||||
| 							mkconst_int(width_hint-1, true), mkconst_int(0, true))); | ||||
| 
 | ||||
| 					reg->str = stringf("$past$%s:%d$%d$%d", filename.c_str(), location.first_line, myidx, i); | ||||
| 					reg->str = stringf("$past$%s:%d$%d$%d", RTLIL::encode_filename(filename).c_str(), location.first_line, myidx, i); | ||||
| 					reg->is_reg = true; | ||||
| 					reg->is_signed = sign_hint; | ||||
| 
 | ||||
|  | @ -3733,7 +3733,7 @@ skip_dynamic_range_lvalue_expansion:; | |||
| 
 | ||||
| 
 | ||||
| 		std::stringstream sstr; | ||||
| 		sstr << str << "$func$" << filename << ":" << location.first_line << "$" << (autoidx++) << '.'; | ||||
| 		sstr << str << "$func$" << RTLIL::encode_filename(filename) << ":" << location.first_line << "$" << (autoidx++) << '.'; | ||||
| 		std::string prefix = sstr.str(); | ||||
| 
 | ||||
| 		AstNode *decl = current_scope[str]; | ||||
|  | @ -4586,7 +4586,7 @@ static void mark_memories_assign_lhs_complex(dict<AstNode*, pool<std::string>> & | |||
| 	if (that->type == AST_IDENTIFIER && that->id2ast && that->id2ast->type == AST_MEMORY) { | ||||
| 		AstNode *mem = that->id2ast; | ||||
| 		if (!(mem2reg_candidates[mem] & AstNode::MEM2REG_FL_CMPLX_LHS)) | ||||
| 			mem2reg_places[mem].insert(stringf("%s:%d", that->filename.c_str(), that->location.first_line)); | ||||
| 			mem2reg_places[mem].insert(stringf("%s:%d", RTLIL::encode_filename(that->filename).c_str(), that->location.first_line)); | ||||
| 		mem2reg_candidates[mem] |= AstNode::MEM2REG_FL_CMPLX_LHS; | ||||
| 	} | ||||
| } | ||||
|  | @ -4614,14 +4614,14 @@ void AstNode::mem2reg_as_needed_pass1(dict<AstNode*, pool<std::string>> &mem2reg | |||
| 			// activate mem2reg if this is assigned in an async proc
 | ||||
| 			if (flags & AstNode::MEM2REG_FL_ASYNC) { | ||||
| 				if (!(mem2reg_candidates[mem] & AstNode::MEM2REG_FL_SET_ASYNC)) | ||||
| 					mem2reg_places[mem].insert(stringf("%s:%d", filename.c_str(), location.first_line)); | ||||
| 					mem2reg_places[mem].insert(stringf("%s:%d", RTLIL::encode_filename(filename).c_str(), location.first_line)); | ||||
| 				mem2reg_candidates[mem] |= AstNode::MEM2REG_FL_SET_ASYNC; | ||||
| 			} | ||||
| 
 | ||||
| 			// remember if this is assigned blocking (=)
 | ||||
| 			if (type == AST_ASSIGN_EQ) { | ||||
| 				if (!(proc_flags[mem] & AstNode::MEM2REG_FL_EQ1)) | ||||
| 					mem2reg_places[mem].insert(stringf("%s:%d", filename.c_str(), location.first_line)); | ||||
| 					mem2reg_places[mem].insert(stringf("%s:%d", RTLIL::encode_filename(filename).c_str(), location.first_line)); | ||||
| 				proc_flags[mem] |= AstNode::MEM2REG_FL_EQ1; | ||||
| 			} | ||||
| 
 | ||||
|  | @ -4638,11 +4638,11 @@ void AstNode::mem2reg_as_needed_pass1(dict<AstNode*, pool<std::string>> &mem2reg | |||
| 			// remember where this is
 | ||||
| 			if (flags & MEM2REG_FL_INIT) { | ||||
| 				if (!(mem2reg_candidates[mem] & AstNode::MEM2REG_FL_SET_INIT)) | ||||
| 					mem2reg_places[mem].insert(stringf("%s:%d", filename.c_str(), location.first_line)); | ||||
| 					mem2reg_places[mem].insert(stringf("%s:%d", RTLIL::encode_filename(filename).c_str(), location.first_line)); | ||||
| 				mem2reg_candidates[mem] |= AstNode::MEM2REG_FL_SET_INIT; | ||||
| 			} else { | ||||
| 				if (!(mem2reg_candidates[mem] & AstNode::MEM2REG_FL_SET_ELSE)) | ||||
| 					mem2reg_places[mem].insert(stringf("%s:%d", filename.c_str(), location.first_line)); | ||||
| 					mem2reg_places[mem].insert(stringf("%s:%d", RTLIL::encode_filename(filename).c_str(), location.first_line)); | ||||
| 				mem2reg_candidates[mem] |= AstNode::MEM2REG_FL_SET_ELSE; | ||||
| 			} | ||||
| 		} | ||||
|  | @ -4656,7 +4656,7 @@ void AstNode::mem2reg_as_needed_pass1(dict<AstNode*, pool<std::string>> &mem2reg | |||
| 
 | ||||
| 		// flag if used after blocking assignment (in same proc)
 | ||||
| 		if ((proc_flags[mem] & AstNode::MEM2REG_FL_EQ1) && !(mem2reg_candidates[mem] & AstNode::MEM2REG_FL_EQ2)) { | ||||
| 			mem2reg_places[mem].insert(stringf("%s:%d", filename.c_str(), location.first_line)); | ||||
| 			mem2reg_places[mem].insert(stringf("%s:%d", RTLIL::encode_filename(filename).c_str(), location.first_line)); | ||||
| 			mem2reg_candidates[mem] |= AstNode::MEM2REG_FL_EQ2; | ||||
| 		} | ||||
| 	} | ||||
|  | @ -4846,7 +4846,7 @@ bool AstNode::mem2reg_as_needed_pass2(pool<AstNode*> &mem2reg_set, AstNode *mod, | |||
| 			children[0]->children[0]->children[0]->type != AST_CONSTANT) | ||||
| 	{ | ||||
| 		std::stringstream sstr; | ||||
| 		sstr << "$mem2reg_wr$" << children[0]->str << "$" << filename << ":" << location.first_line << "$" << (autoidx++); | ||||
| 		sstr << "$mem2reg_wr$" << children[0]->str << "$" << RTLIL::encode_filename(filename) << ":" << location.first_line << "$" << (autoidx++); | ||||
| 		std::string id_addr = sstr.str() + "_ADDR", id_data = sstr.str() + "_DATA"; | ||||
| 
 | ||||
| 		int mem_width, mem_size, addr_bits; | ||||
|  | @ -4962,7 +4962,7 @@ bool AstNode::mem2reg_as_needed_pass2(pool<AstNode*> &mem2reg_set, AstNode *mod, | |||
| 		else | ||||
| 		{ | ||||
| 			std::stringstream sstr; | ||||
| 			sstr << "$mem2reg_rd$" << str << "$" << filename << ":" << location.first_line << "$" << (autoidx++); | ||||
| 			sstr << "$mem2reg_rd$" << str << "$" << RTLIL::encode_filename(filename) << ":" << location.first_line << "$" << (autoidx++); | ||||
| 			std::string id_addr = sstr.str() + "_ADDR", id_data = sstr.str() + "_DATA"; | ||||
| 
 | ||||
| 			int mem_width, mem_size, addr_bits; | ||||
|  |  | |||
		Loading…
	
	Add table
		Add a link
		
	
		Reference in a new issue