From 91cd382f8bb06c19c89742f8c56eb6187ef28d19 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Tue, 18 Mar 2025 13:25:10 +0100 Subject: [PATCH 1/2] macc: Rename 'ports' to 'terms' throughout codebase --- kernel/consteval.h | 2 +- kernel/macc.h | 56 ++++++++++++++++++------------------- kernel/satgen.cc | 2 +- passes/opt/share.cc | 58 +++++++++++++++++++-------------------- passes/techmap/alumacc.cc | 52 +++++++++++++++++------------------ passes/techmap/booth.cc | 6 ++-- passes/techmap/maccmap.cc | 54 ++++++++++++++++++------------------ passes/tests/test_cell.cc | 12 ++++---- 8 files changed, 121 insertions(+), 121 deletions(-) diff --git a/kernel/consteval.h b/kernel/consteval.h index 05e94ab86..844120ef0 100644 --- a/kernel/consteval.h +++ b/kernel/consteval.h @@ -315,7 +315,7 @@ struct ConstEval Macc macc; macc.from_cell(cell); - for (auto &port : macc.ports) { + for (auto &port : macc.terms) { if (!eval(port.in_a, undef, cell)) return false; if (!eval(port.in_b, undef, cell)) diff --git a/kernel/macc.h b/kernel/macc.h index 5fc6036ed..ceda1dceb 100644 --- a/kernel/macc.h +++ b/kernel/macc.h @@ -26,18 +26,18 @@ YOSYS_NAMESPACE_BEGIN struct Macc { - struct port_t { + struct term_t { RTLIL::SigSpec in_a, in_b; bool is_signed, do_subtract; }; - std::vector ports; + std::vector terms; void optimize(int width) { - std::vector new_ports; + std::vector new_terms; RTLIL::Const off(0, width); - for (auto &port : ports) + for (auto &port : terms) { if (GetSize(port.in_a) == 0 && GetSize(port.in_b) == 0) continue; @@ -68,25 +68,25 @@ struct Macc port.in_b.remove(GetSize(port.in_b)-1); } - new_ports.push_back(port); + new_terms.push_back(port); } if (off.as_bool()) { - port_t port; + term_t port; port.in_a = off; port.is_signed = false; port.do_subtract = false; - new_ports.push_back(port); + new_terms.push_back(port); } - new_ports.swap(ports); + new_terms.swap(terms); } void from_cell_v1(RTLIL::Cell *cell) { RTLIL::SigSpec port_a = cell->getPort(ID::A); - ports.clear(); + terms.clear(); auto config_bits = cell->getParam(ID::CONFIG); int config_cursor = 0; @@ -105,7 +105,7 @@ struct Macc { log_assert(config_cursor + 2 + 2*num_bits <= config_width); - port_t this_port; + term_t this_port; this_port.is_signed = config_bits[config_cursor++] == State::S1; this_port.do_subtract = config_bits[config_cursor++] == State::S1; @@ -126,11 +126,11 @@ struct Macc port_a_cursor += size_b; if (size_a || size_b) - ports.push_back(this_port); + terms.push_back(this_port); } for (auto bit : cell->getPort(ID::B)) - ports.push_back(port_t{{bit}, {}, false, false}); + terms.push_back(term_t{{bit}, {}, false, false}); log_assert(config_cursor == config_width); log_assert(port_a_cursor == GetSize(port_a)); @@ -148,7 +148,7 @@ struct Macc RTLIL::SigSpec port_b = cell->getPort(ID::B); RTLIL::SigSpec port_c = cell->getPort(ID::C); - ports.clear(); + terms.clear(); int nproducts = cell->getParam(ID::NPRODUCTS).as_int(); const Const &product_neg = cell->getParam(ID::PRODUCT_NEGATED); @@ -158,7 +158,7 @@ struct Macc const Const &b_signed = cell->getParam(ID::B_SIGNED); int ai = 0, bi = 0; for (int i = 0; i < nproducts; i++) { - port_t term; + term_t term; log_assert(a_signed[i] == b_signed[i]); term.is_signed = (a_signed[i] == State::S1); @@ -171,7 +171,7 @@ struct Macc bi += b_width; term.do_subtract = (product_neg[i] == State::S1); - ports.push_back(term); + terms.push_back(term); } log_assert(port_a.size() == ai); log_assert(port_b.size() == bi); @@ -182,7 +182,7 @@ struct Macc const Const &c_signed = cell->getParam(ID::C_SIGNED); int ci = 0; for (int i = 0; i < naddends; i++) { - port_t term; + term_t term; term.is_signed = (c_signed[i] == State::S1); int c_width = c_widths.extract(16 * i, 16).as_int(false); @@ -191,7 +191,7 @@ struct Macc ci += c_width; term.do_subtract = (addend_neg[i] == State::S1); - ports.push_back(term); + terms.push_back(term); } log_assert(port_c.size() == ci); } @@ -205,23 +205,23 @@ struct Macc Const c_signed, c_widths, addend_negated; SigSpec a, b, c; - for (int i = 0; i < (int) ports.size(); i++) { - SigSpec term_a = ports[i].in_a, term_b = ports[i].in_b; + for (int i = 0; i < (int) terms.size(); i++) { + SigSpec term_a = terms[i].in_a, term_b = terms[i].in_b; if (term_b.empty()) { // addend c_widths.append(Const(term_a.size(), 16)); - c_signed.append(ports[i].is_signed ? RTLIL::S1 : RTLIL::S0); - addend_negated.append(ports[i].do_subtract ? RTLIL::S1 : RTLIL::S0); + c_signed.append(terms[i].is_signed ? RTLIL::S1 : RTLIL::S0); + addend_negated.append(terms[i].do_subtract ? RTLIL::S1 : RTLIL::S0); c.append(term_a); naddends++; } else { // product a_widths.append(Const(term_a.size(), 16)); b_widths.append(Const(term_b.size(), 16)); - a_signed.append(ports[i].is_signed ? RTLIL::S1 : RTLIL::S0); - b_signed.append(ports[i].is_signed ? RTLIL::S1 : RTLIL::S0); - product_negated.append(ports[i].do_subtract ? RTLIL::S1 : RTLIL::S0); + a_signed.append(terms[i].is_signed ? RTLIL::S1 : RTLIL::S0); + b_signed.append(terms[i].is_signed ? RTLIL::S1 : RTLIL::S0); + product_negated.append(terms[i].do_subtract ? RTLIL::S1 : RTLIL::S0); a.append(term_a); b.append(term_b); nproducts++; @@ -265,7 +265,7 @@ struct Macc for (auto &bit : result.bits()) bit = State::S0; - for (auto &port : ports) + for (auto &port : terms) { if (!port.in_a.is_fully_const() || !port.in_b.is_fully_const()) return false; @@ -287,9 +287,9 @@ struct Macc bool is_simple_product() { - return ports.size() == 1 && - !ports[0].in_b.empty() && - !ports[0].do_subtract; + return terms.size() == 1 && + !terms[0].in_b.empty() && + !terms[0].do_subtract; } Macc(RTLIL::Cell *cell = nullptr) diff --git a/kernel/satgen.cc b/kernel/satgen.cc index 9e5fa9111..13f243b14 100644 --- a/kernel/satgen.cc +++ b/kernel/satgen.cc @@ -750,7 +750,7 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep) std::vector tmp(GetSize(y), ez->CONST_FALSE); - for (auto &port : macc.ports) + for (auto &port : macc.terms) { std::vector in_a = importDefSigSpec(port.in_a, timestep); std::vector in_b = importDefSigSpec(port.in_b, timestep); diff --git a/passes/opt/share.cc b/passes/opt/share.cc index 57a52969b..14e184a99 100644 --- a/passes/opt/share.cc +++ b/passes/opt/share.cc @@ -110,7 +110,7 @@ struct ShareWorker // Code for sharing and comparing MACC cells // --------------------------------------------------- - static int bits_macc_port(const Macc::port_t &p, int width) + static int bits_macc_term(const Macc::term_t &p, int width) { if (GetSize(p.in_a) == 0 || GetSize(p.in_b) == 0) return min(max(GetSize(p.in_a), GetSize(p.in_b)), width); @@ -120,8 +120,8 @@ struct ShareWorker static int bits_macc(const Macc &m, int width) { int bits = 0; - for (auto &p : m.ports) - bits += bits_macc_port(p, width); + for (auto &p : m.terms) + bits += bits_macc_term(p, width); return bits; } @@ -132,7 +132,7 @@ struct ShareWorker return bits_macc(m, width); } - static bool cmp_macc_ports(const Macc::port_t &p1, const Macc::port_t &p2) + static bool cmp_macc_ports(const Macc::term_t &p1, const Macc::term_t &p2) { bool mul1 = GetSize(p1.in_a) && GetSize(p1.in_b); bool mul2 = GetSize(p2.in_a) && GetSize(p2.in_b); @@ -161,7 +161,7 @@ struct ShareWorker return false; } - int share_macc_ports(Macc::port_t &p1, Macc::port_t &p2, int w1, int w2, + int share_macc_ports(Macc::term_t &p1, Macc::term_t &p2, int w1, int w2, RTLIL::SigSpec act = RTLIL::SigSpec(), Macc *supermacc = nullptr, pool *supercell_aux = nullptr) { if (p1.do_subtract != p2.do_subtract) @@ -216,12 +216,12 @@ struct ShareWorker supercell_aux->insert(module->addMux(NEW_ID, sig_b2, sig_b1, act, sig_b)); } - Macc::port_t p; + Macc::term_t p; p.in_a = sig_a; p.in_b = sig_b; p.is_signed = force_signed; p.do_subtract = p1.do_subtract; - supermacc->ports.push_back(p); + supermacc->terms.push_back(p); } int score = 1000 + abs(GetSize(p1.in_a) - GetSize(p2.in_a)) * max(abs(GetSize(p1.in_b) - GetSize(p2.in_b)), 1); @@ -248,15 +248,15 @@ struct ShareWorker m1.optimize(w1); m2.optimize(w2); - std::sort(m1.ports.begin(), m1.ports.end(), cmp_macc_ports); - std::sort(m2.ports.begin(), m2.ports.end(), cmp_macc_ports); + std::sort(m1.terms.begin(), m1.terms.end(), cmp_macc_ports); + std::sort(m2.terms.begin(), m2.terms.end(), cmp_macc_ports); std::set m1_unmapped, m2_unmapped; - for (int i = 0; i < GetSize(m1.ports); i++) + for (int i = 0; i < GetSize(m1.terms); i++) m1_unmapped.insert(i); - for (int i = 0; i < GetSize(m2.ports); i++) + for (int i = 0; i < GetSize(m2.terms); i++) m2_unmapped.insert(i); while (1) @@ -265,7 +265,7 @@ struct ShareWorker for (int i : m1_unmapped) for (int j : m2_unmapped) { - int score = share_macc_ports(m1.ports[i], m2.ports[j], w1, w2); + int score = share_macc_ports(m1.terms[i], m2.terms[j], w1, w2); if (score >= 0 && (best_i < 0 || best_score > score)) best_i = i, best_j = j, best_score = score; } @@ -273,55 +273,55 @@ struct ShareWorker if (best_i >= 0) { m1_unmapped.erase(best_i); m2_unmapped.erase(best_j); - share_macc_ports(m1.ports[best_i], m2.ports[best_j], w1, w2, act, &supermacc, supercell_aux); + share_macc_ports(m1.terms[best_i], m2.terms[best_j], w1, w2, act, &supermacc, supercell_aux); } else break; } for (int i : m1_unmapped) { - RTLIL::SigSpec sig_a = m1.ports[i].in_a; - RTLIL::SigSpec sig_b = m1.ports[i].in_b; + RTLIL::SigSpec sig_a = m1.terms[i].in_a; + RTLIL::SigSpec sig_b = m1.terms[i].in_b; if (supercell_aux && GetSize(sig_a)) { sig_a = module->addWire(NEW_ID, GetSize(sig_a)); - supercell_aux->insert(module->addMux(NEW_ID, RTLIL::SigSpec(0, GetSize(sig_a)), m1.ports[i].in_a, act, sig_a)); + supercell_aux->insert(module->addMux(NEW_ID, RTLIL::SigSpec(0, GetSize(sig_a)), m1.terms[i].in_a, act, sig_a)); } if (supercell_aux && GetSize(sig_b)) { sig_b = module->addWire(NEW_ID, GetSize(sig_b)); - supercell_aux->insert(module->addMux(NEW_ID, RTLIL::SigSpec(0, GetSize(sig_b)), m1.ports[i].in_b, act, sig_b)); + supercell_aux->insert(module->addMux(NEW_ID, RTLIL::SigSpec(0, GetSize(sig_b)), m1.terms[i].in_b, act, sig_b)); } - Macc::port_t p; + Macc::term_t p; p.in_a = sig_a; p.in_b = sig_b; - p.is_signed = m1.ports[i].is_signed; - p.do_subtract = m1.ports[i].do_subtract; - supermacc.ports.push_back(p); + p.is_signed = m1.terms[i].is_signed; + p.do_subtract = m1.terms[i].do_subtract; + supermacc.terms.push_back(p); } for (int i : m2_unmapped) { - RTLIL::SigSpec sig_a = m2.ports[i].in_a; - RTLIL::SigSpec sig_b = m2.ports[i].in_b; + RTLIL::SigSpec sig_a = m2.terms[i].in_a; + RTLIL::SigSpec sig_b = m2.terms[i].in_b; if (supercell_aux && GetSize(sig_a)) { sig_a = module->addWire(NEW_ID, GetSize(sig_a)); - supercell_aux->insert(module->addMux(NEW_ID, m2.ports[i].in_a, RTLIL::SigSpec(0, GetSize(sig_a)), act, sig_a)); + supercell_aux->insert(module->addMux(NEW_ID, m2.terms[i].in_a, RTLIL::SigSpec(0, GetSize(sig_a)), act, sig_a)); } if (supercell_aux && GetSize(sig_b)) { sig_b = module->addWire(NEW_ID, GetSize(sig_b)); - supercell_aux->insert(module->addMux(NEW_ID, m2.ports[i].in_b, RTLIL::SigSpec(0, GetSize(sig_b)), act, sig_b)); + supercell_aux->insert(module->addMux(NEW_ID, m2.terms[i].in_b, RTLIL::SigSpec(0, GetSize(sig_b)), act, sig_b)); } - Macc::port_t p; + Macc::term_t p; p.in_a = sig_a; p.in_b = sig_b; - p.is_signed = m2.ports[i].is_signed; - p.do_subtract = m2.ports[i].do_subtract; - supermacc.ports.push_back(p); + p.is_signed = m2.terms[i].is_signed; + p.do_subtract = m2.terms[i].do_subtract; + supermacc.terms.push_back(p); } if (supercell) diff --git a/passes/techmap/alumacc.cc b/passes/techmap/alumacc.cc index 591c51c74..3dc54e8bb 100644 --- a/passes/techmap/alumacc.cc +++ b/passes/techmap/alumacc.cc @@ -142,7 +142,7 @@ struct AlumaccWorker log(" creating $macc model for %s (%s).\n", log_id(cell), log_id(cell->type)); maccnode_t *n = new maccnode_t; - Macc::port_t new_port; + Macc::term_t new_term; n->cell = cell; n->y = sigmap(cell->getPort(ID::Y)); @@ -153,32 +153,32 @@ struct AlumaccWorker if (cell->type.in(ID($pos), ID($neg))) { - new_port.in_a = sigmap(cell->getPort(ID::A)); - new_port.is_signed = cell->getParam(ID::A_SIGNED).as_bool(); - new_port.do_subtract = cell->type == ID($neg); - n->macc.ports.push_back(new_port); + new_term.in_a = sigmap(cell->getPort(ID::A)); + new_term.is_signed = cell->getParam(ID::A_SIGNED).as_bool(); + new_term.do_subtract = cell->type == ID($neg); + n->macc.terms.push_back(new_term); } if (cell->type.in(ID($add), ID($sub))) { - new_port.in_a = sigmap(cell->getPort(ID::A)); - new_port.is_signed = cell->getParam(ID::A_SIGNED).as_bool(); - new_port.do_subtract = false; - n->macc.ports.push_back(new_port); + new_term.in_a = sigmap(cell->getPort(ID::A)); + new_term.is_signed = cell->getParam(ID::A_SIGNED).as_bool(); + new_term.do_subtract = false; + n->macc.terms.push_back(new_term); - new_port.in_a = sigmap(cell->getPort(ID::B)); - new_port.is_signed = cell->getParam(ID::B_SIGNED).as_bool(); - new_port.do_subtract = cell->type == ID($sub); - n->macc.ports.push_back(new_port); + new_term.in_a = sigmap(cell->getPort(ID::B)); + new_term.is_signed = cell->getParam(ID::B_SIGNED).as_bool(); + new_term.do_subtract = cell->type == ID($sub); + n->macc.terms.push_back(new_term); } if (cell->type.in(ID($mul))) { - new_port.in_a = sigmap(cell->getPort(ID::A)); - new_port.in_b = sigmap(cell->getPort(ID::B)); - new_port.is_signed = cell->getParam(ID::A_SIGNED).as_bool(); - new_port.do_subtract = false; - n->macc.ports.push_back(new_port); + new_term.in_a = sigmap(cell->getPort(ID::A)); + new_term.in_b = sigmap(cell->getPort(ID::B)); + new_term.is_signed = cell->getParam(ID::A_SIGNED).as_bool(); + new_term.do_subtract = false; + n->macc.terms.push_back(new_term); } log_assert(sig_macc.count(n->y) == 0); @@ -190,7 +190,7 @@ struct AlumaccWorker { std::vector port_sizes; - for (auto &port : macc.ports) { + for (auto &port : macc.terms) { if (port.is_signed != is_signed) return true; if (!port.is_signed && port.do_subtract) @@ -235,9 +235,9 @@ struct AlumaccWorker if (delete_nodes.count(n)) continue; - for (int i = 0; i < GetSize(n->macc.ports); i++) + for (int i = 0; i < GetSize(n->macc.terms); i++) { - auto &port = n->macc.ports[i]; + auto &port = n->macc.terms[i]; if (GetSize(port.in_b) > 0 || sig_macc.count(port.in_a) == 0) continue; @@ -253,13 +253,13 @@ struct AlumaccWorker log(" merging $macc model for %s into %s.\n", log_id(other_n->cell), log_id(n->cell)); bool do_subtract = port.do_subtract; - for (int j = 0; j < GetSize(other_n->macc.ports); j++) { + for (int j = 0; j < GetSize(other_n->macc.terms); j++) { if (do_subtract) - other_n->macc.ports[j].do_subtract = !other_n->macc.ports[j].do_subtract; + other_n->macc.terms[j].do_subtract = !other_n->macc.terms[j].do_subtract; if (j == 0) - n->macc.ports[i--] = other_n->macc.ports[j]; + n->macc.terms[i--] = other_n->macc.terms[j]; else - n->macc.ports.push_back(other_n->macc.ports[j]); + n->macc.terms.push_back(other_n->macc.terms[j]); } delete_nodes.insert(other_n); @@ -288,7 +288,7 @@ struct AlumaccWorker bool subtract_b = false; alunode_t *alunode; - for (auto &port : n->macc.ports) + for (auto &port : n->macc.terms) if (GetSize(port.in_b) > 0) { goto next_macc; } else if (GetSize(port.in_a) == 1 && !port.is_signed && !port.do_subtract) { diff --git a/passes/techmap/booth.cc b/passes/techmap/booth.cc index cd9012e6c..a692b99fe 100644 --- a/passes/techmap/booth.cc +++ b/passes/techmap/booth.cc @@ -227,9 +227,9 @@ struct BoothPassWorker { continue; } - A = macc.ports[0].in_a; - B = macc.ports[0].in_b; - is_signed = macc.ports[0].is_signed; + A = macc.terms[0].in_a; + B = macc.terms[0].in_b; + is_signed = macc.terms[0].is_signed; Y = cell->getPort(ID::Y); } else { continue; diff --git a/passes/techmap/maccmap.cc b/passes/techmap/maccmap.cc index 3dde92438..42b615002 100644 --- a/passes/techmap/maccmap.cc +++ b/passes/techmap/maccmap.cc @@ -278,42 +278,42 @@ void maccmap(RTLIL::Module *module, RTLIL::Cell *cell, bool unmap) return; } - for (auto &port : macc.ports) - if (GetSize(port.in_b) == 0) - log(" %s %s (%d bits, %s)\n", port.do_subtract ? "sub" : "add", log_signal(port.in_a), - GetSize(port.in_a), port.is_signed ? "signed" : "unsigned"); + for (auto &term : macc.terms) + if (GetSize(term.in_b) == 0) + log(" %s %s (%d bits, %s)\n", term.do_subtract ? "sub" : "add", log_signal(term.in_a), + GetSize(term.in_a), term.is_signed ? "signed" : "unsigned"); else - log(" %s %s * %s (%dx%d bits, %s)\n", port.do_subtract ? "sub" : "add", log_signal(port.in_a), log_signal(port.in_b), - GetSize(port.in_a), GetSize(port.in_b), port.is_signed ? "signed" : "unsigned"); + log(" %s %s * %s (%dx%d bits, %s)\n", term.do_subtract ? "sub" : "add", log_signal(term.in_a), log_signal(term.in_b), + GetSize(term.in_a), GetSize(term.in_b), term.is_signed ? "signed" : "unsigned"); if (unmap) { typedef std::pair summand_t; std::vector summands; - RTLIL::SigSpec bit_ports; + RTLIL::SigSpec bit_terms; - for (auto &port : macc.ports) { + for (auto &term : macc.terms) { summand_t this_summand; - if (GetSize(port.in_b)) { + if (GetSize(term.in_b)) { this_summand.first = module->addWire(NEW_ID, width); - module->addMul(NEW_ID, port.in_a, port.in_b, this_summand.first, port.is_signed); - } else if (GetSize(port.in_a) == 1 && GetSize(port.in_b) == 0 && !port.is_signed && !port.do_subtract) { - // Mimic old 'bit_ports' treatment in case it's relevant for performance, + module->addMul(NEW_ID, term.in_a, term.in_b, this_summand.first, term.is_signed); + } else if (GetSize(term.in_a) == 1 && GetSize(term.in_b) == 0 && !term.is_signed && !term.do_subtract) { + // Mimic old 'bit_terms' treatment in case it's relevant for performance, // i.e. defer single-bit summands to be the last ones - bit_ports.append(port.in_a); + bit_terms.append(term.in_a); continue; - } else if (GetSize(port.in_a) != width) { + } else if (GetSize(term.in_a) != width) { this_summand.first = module->addWire(NEW_ID, width); - module->addPos(NEW_ID, port.in_a, this_summand.first, port.is_signed); + module->addPos(NEW_ID, term.in_a, this_summand.first, term.is_signed); } else { - this_summand.first = port.in_a; + this_summand.first = term.in_a; } - this_summand.second = port.do_subtract; + this_summand.second = term.do_subtract; summands.push_back(this_summand); } - for (auto &bit : bit_ports) + for (auto &bit : bit_terms) summands.push_back(summand_t(bit, false)); if (GetSize(summands) == 0) @@ -350,20 +350,20 @@ void maccmap(RTLIL::Module *module, RTLIL::Cell *cell, bool unmap) else { MaccmapWorker worker(module, width); - RTLIL::SigSpec bit_ports; + RTLIL::SigSpec bit_terms; - for (auto &port : macc.ports) { - // Mimic old 'bit_ports' treatment in case it's relevant for performance, + for (auto &term : macc.terms) { + // Mimic old 'bit_terms' treatment in case it's relevant for performance, // i.e. defer single-bit summands to be the last ones - if (GetSize(port.in_a) == 1 && GetSize(port.in_b) == 0 && !port.is_signed && !port.do_subtract) - bit_ports.append(port.in_a); - else if (GetSize(port.in_b) == 0) - worker.add(port.in_a, port.is_signed, port.do_subtract); + if (GetSize(term.in_a) == 1 && GetSize(term.in_b) == 0 && !term.is_signed && !term.do_subtract) + bit_terms.append(term.in_a); + else if (GetSize(term.in_b) == 0) + worker.add(term.in_a, term.is_signed, term.do_subtract); else - worker.add(port.in_a, port.in_b, port.is_signed, port.do_subtract); + worker.add(term.in_a, term.in_b, term.is_signed, term.do_subtract); } - for (auto bit : bit_ports) + for (auto bit : bit_terms) worker.add(bit, 0); module->connect(cell->getPort(ID::Y), worker.synth()); diff --git a/passes/tests/test_cell.cc b/passes/tests/test_cell.cc index 39b7ccd3a..a34eafc2f 100644 --- a/passes/tests/test_cell.cc +++ b/passes/tests/test_cell.cc @@ -189,17 +189,17 @@ static RTLIL::Cell* create_gold_module(RTLIL::Design *design, RTLIL::IdString ce } else size_b = 0; - Macc::port_t this_port; + Macc::term_t this_term; wire_a->width += size_a; - this_port.in_a = RTLIL::SigSpec(wire_a, wire_a->width - size_a, size_a); + this_term.in_a = RTLIL::SigSpec(wire_a, wire_a->width - size_a, size_a); wire_a->width += size_b; - this_port.in_b = RTLIL::SigSpec(wire_a, wire_a->width - size_b, size_b); + this_term.in_b = RTLIL::SigSpec(wire_a, wire_a->width - size_b, size_b); - this_port.is_signed = xorshift32(2) == 1; - this_port.do_subtract = xorshift32(2) == 1; - macc.ports.push_back(this_port); + this_term.is_signed = xorshift32(2) == 1; + this_term.do_subtract = xorshift32(2) == 1; + macc.terms.push_back(this_term); } // Macc::to_cell sets the input ports macc.to_cell(cell); From 251285be4c086eba80cafe637029218bb2e8f2a7 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Tue, 18 Mar 2025 13:51:09 +0100 Subject: [PATCH 2/2] cost: Add `$mem_v2`, `$macc_v2` estimates --- kernel/cost.cc | 24 ++++++++++++++++++++++-- 1 file changed, 22 insertions(+), 2 deletions(-) diff --git a/kernel/cost.cc b/kernel/cost.cc index 5d897ab7a..985220f14 100644 --- a/kernel/cost.cc +++ b/kernel/cost.cc @@ -1,4 +1,5 @@ #include "kernel/cost.h" +#include "kernel/macc.h" USING_YOSYS_NAMESPACE @@ -148,6 +149,9 @@ unsigned int CellCosts::get(RTLIL::Cell *cell) log_assert(cell->hasPort(ID::Q) && "Weird flip flop"); log_debug("%s is ff\n", cell->name.c_str()); return cell->getParam(ID::WIDTH).as_int(); + } else if (cell->type.in(ID($mem), ID($mem_v2))) { + log_debug("%s is mem\n", cell->name.c_str()); + return cell->getParam(ID::WIDTH).as_int() * cell->getParam(ID::SIZE).as_int(); } else if (y_coef(cell->type)) { // linear with Y_WIDTH or WIDTH log_assert((cell->hasParam(ID::Y_WIDTH) || cell->hasParam(ID::WIDTH)) && "Unknown width"); @@ -173,6 +177,22 @@ unsigned int CellCosts::get(RTLIL::Cell *cell) unsigned int coef = cell->type == ID($mul) ? 3 : 5; log_debug("%s coef*(sum**2) %d * %d\n", cell->name.c_str(), coef, sum * sum); return coef * sum * sum; + } else if (cell->type.in(ID($macc), ID($macc_v2))) { + // quadratic per term + unsigned int cost_sum = 0; + Macc macc; + macc.from_cell(cell); + unsigned int y_width = cell->getParam(ID::Y_WIDTH).as_int(); + for (auto &term: macc.terms) { + if (term.in_b.empty()) { + // neglect addends + continue; + } + unsigned a_width = term.in_a.size(), b_width = term.in_b.size(); + unsigned int sum = a_width + b_width + std::min(y_width, a_width + b_width); + cost_sum += 3 * sum * sum; + } + return cost_sum; } else if (cell->type == ID($lut)) { int width = cell->getParam(ID::WIDTH).as_int(); unsigned int cost = 1U << (unsigned int)width; @@ -187,8 +207,8 @@ unsigned int CellCosts::get(RTLIL::Cell *cell) log_debug("%s is free\n", cell->name.c_str()); return 0; } - // TODO: $fsm $mem.* $macc - // ignored: $pow + // TODO: $fsm + // ignored: $pow $memrd $memwr $meminit (and v2 counterparts) log_warning("Can't determine cost of %s cell (%d parameters).\n", log_id(cell->type), GetSize(cell->parameters)); return 1;