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Merge 1d30c66a7f into 71de666003

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Johann Glaser 2013-03-18 14:12:45 -07:00
parent 71de666003 1d30c66a7f
commit 6c1f21cb62
3 changed files with 27 additions and 9 deletions
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25
README
View file

@ -40,14 +40,25 @@ or the 2-clause BSD license).
Getting Started
===============
To build Yosys simply type 'make' in this directory. You need
a C++ compiler with C++11 support (up-to-date CLANG or GCC is
recommended) and some standard tools such as GNU Flex, GNU Bison,
and GNU Make. It might be necessary to make some changes to
the config section of the Makefile. The extensive tests require
Icarus Verilog.
You need a C++ compiler with C++11 support (up-to-date CLANG or GCC is
recommended) and some standard tools such as GNU Flex, GNU Bison, and
GNU Make. The extensive tests require Icarus Verilog.
To configure the build system to use a specific set of compiler and
build configuration, use one of
$ make config-clang-debug
$ make config-gcc-debug
$ make config-release
For other compilers and build configurations it might be
necessary to make some changes to the config section of the
Makefile.
$ vi Makefile
To build Yosys simply type 'make' in this directory.
$ make
$ make test
$ sudo make install
@ -237,3 +248,5 @@ TODOs / Open Bugs
- Better FSM state encoding
- For pass' "fsm_detect" help: add notes what criteria lets it detect an FSM

4
kernel/register.cc
View file

@ -132,7 +132,7 @@ void Pass::extra_args(std::vector<std::string> args, size_t argidx, RTLIL::Desig
void Pass::call(RTLIL::Design *design, std::string command)
{
std::vector<std::string> args;
char *s = strdup(command.c_str()), *saveptr;
char *s = strdup(command.c_str()), *sstart = s, *saveptr;
s += strspn(s, " \t\r\n");
if (*s == 0 || *s == '#')
return;
@ -160,7 +160,7 @@ void Pass::call(RTLIL::Design *design, std::string command)
} else
args.push_back(str);
}
free(s);
free(sstart);
call(design, args);
}

7
passes/opt/opt_const.cc
View file

@ -113,7 +113,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module)
if (input.match("0 ")) ACTION_DO("\\Y", input.extract(0, 1));
}
if (cell->type == "$_MUX_") {
if (cell->type == "$_MUX_" ||(cell->type == "$mux" && cell->parameters["\\WIDTH"].as_int() == 1)) {
RTLIL::SigSpec input;
input.append(cell->connections["\\S"]);
input.append(cell->connections["\\B"]);
@ -125,6 +125,11 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module)
if (input.match(" 1")) ACTION_DO("\\Y", input.extract(1, 1));
#ifdef MUX_UNDEF_SEL_TO_UNDEF_RESULTS
if (input.match("01 ")) ACTION_DO("\\Y", input.extract(0, 1));
// TODO: "10 " -> replace with "!S" gate
// TODO: "0 " -> replace with "B AND S" gate
// TODO: " 1 " -> replace with "A OR S" gate
// TODO: "1 " -> replace with "B OR !S" gate
// TODO: " 0 " -> replace with "A AND !S" gate
if (input.match(" *")) ACTION_DO_Y(x);
#endif
}