Merge branch 'YosysHQ:main' into master

.gitignore

@@ -7,6 +7,7 @@
 *.gcno
 *~
 __pycache__
+/.cache
 /.cproject
 /.project
 /.settings
@@ -15,6 +16,7 @@ __pycache__
 /qtcreator.config
 /qtcreator.creator
 /qtcreator.creator.user
+/compile_commands.json
 /coverage.info
 /coverage_html
 /Makefile.conf
@@ -52,3 +54,4 @@ __pycache__
 /venv
 /boost
 /ffi
+/*.whl

CHANGELOG

@@ -2,9 +2,23 @@
 List of major changes and improvements between releases
 =======================================================
 
-Yosys 0.51 .. Yosys 0.52-dev
+Yosys 0.52 .. Yosys 0.53-dev
 --------------------------
 
+Yosys 0.51 .. Yosys 0.52
+--------------------------
+ * New commands and options
+    - Added "-pattern-limit" option to "share" pass to limit analysis effort.
+    - Added "libcache" pass to control caching of technology library 
+      data parsed from liberty files.
+    - Added "read_verilog_file_list" to parse verilog file list.
+
+ * Various
+    - Added $macc_v2 cell.
+    - Improve lexer performance and zlib support for "read_liberty".
+    - opt_expr: optimize pow of 2 cells.
+
+
 Yosys 0.50 .. Yosys 0.51
 --------------------------
  * New commands and options

Makefile

@@ -114,6 +114,12 @@ BISON ?= bison
 STRIP ?= strip
 AWK ?= awk
 
+ifneq ($(shell :; command -v rsync),)
+RSYNC_CP ?= rsync -rc
+else
+RSYNC_CP ?= cp -ru
+endif
+
 ifeq ($(OS), Darwin)
 PLUGIN_LINKFLAGS += -undefined dynamic_lookup
 LINKFLAGS += -rdynamic
@@ -153,7 +159,7 @@ ifeq ($(OS), Haiku)
 CXXFLAGS += -D_DEFAULT_SOURCE
 endif
 
-YOSYS_VER := 0.51+0
+YOSYS_VER := 0.52+0
 YOSYS_MAJOR := $(shell echo $(YOSYS_VER) | cut -d'.' -f1)
 YOSYS_MINOR := $(shell echo $(YOSYS_VER) | cut -d'.' -f2 | cut -d'+' -f1)
 YOSYS_COMMIT := $(shell echo $(YOSYS_VER) | cut -d'+' -f2)
@@ -176,7 +182,7 @@ endif
 OBJS = kernel/version_$(GIT_REV).o
 
 bumpversion:
-	sed -i "/^YOSYS_VER := / s/+[0-9][0-9]*$$/+`git log --oneline c4b5190.. | wc -l`/;" Makefile
+	sed -i "/^YOSYS_VER := / s/+[0-9][0-9]*$$/+`git log --oneline fee39a3.. | wc -l`/;" Makefile
 
 ABCMKARGS = CC="$(CXX)" CXX="$(CXX)" ABC_USE_LIBSTDCXX=1 ABC_USE_NAMESPACE=abc VERBOSE=$(Q)
 
@@ -303,7 +309,7 @@ CXXFLAGS += -std=$(CXXSTD) $(OPT_LEVEL) -D_POSIX_SOURCE -DYOSYS_WIN32_UNIX_DIR
 CXXFLAGS := $(filter-out -fPIC,$(CXXFLAGS))
 LINKFLAGS := $(filter-out -rdynamic,$(LINKFLAGS)) -s
 LIBS := $(filter-out -lrt,$(LIBS))
-ABCMKARGS += ARCHFLAGS="-DABC_USE_STDINT_H -DWIN32_NO_DLL -DHAVE_STRUCT_TIMESPEC -fpermissive -w"
+ABCMKARGS += ARCHFLAGS="-DABC_USE_STDINT_H -DWIN32_NO_DLL -DWIN32 -DHAVE_STRUCT_TIMESPEC -fpermissive -w"
 ABCMKARGS += LIBS="-lpthread -lshlwapi -s" ABC_USE_NO_READLINE=0 CC="i686-w64-mingw32-gcc" CXX="$(CXX)"
 EXE = .exe
 
@@ -313,7 +319,7 @@ CXXFLAGS += -std=$(CXXSTD) $(OPT_LEVEL) -D_POSIX_SOURCE -DYOSYS_WIN32_UNIX_DIR
 CXXFLAGS := $(filter-out -fPIC,$(CXXFLAGS))
 LINKFLAGS := $(filter-out -rdynamic,$(LINKFLAGS)) -s
 LIBS := $(filter-out -lrt,$(LIBS))
-ABCMKARGS += ARCHFLAGS="-DABC_USE_STDINT_H -DWIN32_NO_DLL -DHAVE_STRUCT_TIMESPEC -fpermissive -w"
+ABCMKARGS += ARCHFLAGS="-DABC_USE_STDINT_H -DWIN32_NO_DLL -DWIN32 -DHAVE_STRUCT_TIMESPEC -fpermissive -w"
 ABCMKARGS += LIBS="-lpthread -lshlwapi -s" ABC_USE_NO_READLINE=0 CC="x86_64-w64-mingw32-gcc" CXX="$(CXX)"
 EXE = .exe
 
@@ -341,6 +347,7 @@ ifeq ($(ENABLE_PYOSYS),1)
 LINKFLAGS += $(filter-out -l%,$(shell $(PYTHON_CONFIG) --ldflags))
 LIBS += $(shell $(PYTHON_CONFIG) --libs)
 CXXFLAGS += $(shell $(PYTHON_CONFIG) --includes) -DWITH_PYTHON
+EXTRA_TARGETS += wheel
 
 # Detect name of boost_python library. Some distros use boost_python-py<version>, other boost_python<version>, some only use the major version number, some a concatenation of major and minor version numbers
 CHECK_BOOST_PYTHON = (echo "int main(int argc, char ** argv) {return 0;}" | $(CXX) -xc -o /dev/null $(LINKFLAGS) $(LIBS) -l$(1) - > /dev/null 2>&1 && echo "-l$(1)")
@@ -359,7 +366,7 @@ LIBS += $(BOOST_PYTHON_LIB) -lboost_system -lboost_filesystem
 PY_WRAPPER_FILE = kernel/python_wrappers
 OBJS += $(PY_WRAPPER_FILE).o
 PY_GEN_SCRIPT= py_wrap_generator
-PY_WRAP_INCLUDES := $(shell python$(PYTHON_VERSION) -c "from misc import $(PY_GEN_SCRIPT); $(PY_GEN_SCRIPT).print_includes()")
+PY_WRAP_INCLUDES := $(shell $(PYTHON_EXECUTABLE) -c "from misc import $(PY_GEN_SCRIPT); $(PY_GEN_SCRIPT).print_includes()")
 endif # ENABLE_PYOSYS
 
 ifeq ($(ENABLE_READLINE),1)
@@ -586,7 +593,9 @@ $(eval $(call add_include_file,kernel/fmt.h))
 ifeq ($(ENABLE_ZLIB),1)
 $(eval $(call add_include_file,kernel/fstdata.h))
 endif
+$(eval $(call add_include_file,kernel/gzip.h))
 $(eval $(call add_include_file,kernel/hashlib.h))
+$(eval $(call add_include_file,kernel/io.h))
 $(eval $(call add_include_file,kernel/json.h))
 $(eval $(call add_include_file,kernel/log.h))
 $(eval $(call add_include_file,kernel/macc.h))
@@ -617,7 +626,7 @@ $(eval $(call add_include_file,frontends/ast/ast_binding.h))
 $(eval $(call add_include_file,frontends/blif/blifparse.h))
 $(eval $(call add_include_file,backends/rtlil/rtlil_backend.h))
 
-OBJS += kernel/driver.o kernel/register.o kernel/rtlil.o kernel/log.o kernel/calc.o kernel/yosys.o
+OBJS += kernel/driver.o kernel/register.o kernel/rtlil.o kernel/log.o kernel/calc.o kernel/yosys.o kernel/io.o kernel/gzip.o
 OBJS += kernel/binding.o kernel/tclapi.o
 OBJS += kernel/cellaigs.o kernel/celledges.o kernel/cost.o kernel/satgen.o kernel/scopeinfo.o kernel/qcsat.o kernel/mem.o kernel/ffmerge.o kernel/ff.o kernel/yw.o kernel/json.o kernel/fmt.o kernel/sexpr.o
 OBJS += kernel/drivertools.o kernel/functional.o
@@ -746,7 +755,7 @@ endif
 ifeq ($(ENABLE_PYOSYS),1)
 $(PY_WRAPPER_FILE).cc: misc/$(PY_GEN_SCRIPT).py $(PY_WRAP_INCLUDES)
 	$(Q) mkdir -p $(dir $@)
-	$(P) python$(PYTHON_VERSION) -c "from misc import $(PY_GEN_SCRIPT); $(PY_GEN_SCRIPT).gen_wrappers(\"$(PY_WRAPPER_FILE).cc\")"
+	$(P) $(PYTHON_EXECUTABLE) -c "from misc import $(PY_GEN_SCRIPT); $(PY_GEN_SCRIPT).gen_wrappers(\"$(PY_WRAPPER_FILE).cc\")"
 endif
 
 %.o: %.cpp
@@ -957,6 +966,20 @@ unit-test: libyosys.so
 clean-unit-test:
 	@$(MAKE) -C $(UNITESTPATH) clean
 
+ifeq ($(ENABLE_PYOSYS),1)
+wheel: $(TARGETS)
+	$(PYTHON_EXECUTABLE) -m pip wheel .
+
+install-wheel: wheel
+	$(PYTHON_EXECUTABLE) -m pip install pyosys-$(YOSYS_MAJOR).$(YOSYS_MINOR).$(YOSYS_COMMIT)-*.whl --force-reinstall
+else
+wheel:
+	$(error Pyosys is not enabled. Set ENABLE_PYOSYS=1 to enable it.)
+
+install-wheel:
+	$(error Pyosys is not enabled. Set ENABLE_PYOSYS=1 to enable it.)
+endif
+
 install: $(TARGETS) $(EXTRA_TARGETS)
 	$(INSTALL_SUDO) mkdir -p $(DESTDIR)$(BINDIR)
 	$(INSTALL_SUDO) cp $(filter-out libyosys.so,$(TARGETS)) $(DESTDIR)$(BINDIR)
@@ -976,9 +999,7 @@ ifeq ($(ENABLE_LIBYOSYS),1)
 	$(INSTALL_SUDO) cp libyosys.so $(DESTDIR)$(LIBDIR)/
 	$(INSTALL_SUDO) $(STRIP) -S $(DESTDIR)$(LIBDIR)/libyosys.so
 ifeq ($(ENABLE_PYOSYS),1)
-	$(INSTALL_SUDO) mkdir -p $(DESTDIR)$(PYTHON_DESTDIR)/$(subst -,_,$(PROGRAM_PREFIX))pyosys
-	$(INSTALL_SUDO) cp libyosys.so $(DESTDIR)$(PYTHON_DESTDIR)/$(subst -,_,$(PROGRAM_PREFIX))pyosys/libyosys.so
-	$(INSTALL_SUDO) cp misc/__init__.py $(DESTDIR)$(PYTHON_DESTDIR)/$(subst -,_,$(PROGRAM_PREFIX))pyosys/
+	$(INSTALL_SUDO) @$(MAKE) install-wheel
 endif
 endif
 ifeq ($(ENABLE_PLUGINS),1)
@@ -994,9 +1015,7 @@ uninstall:
 ifeq ($(ENABLE_LIBYOSYS),1)
 	$(INSTALL_SUDO) rm -vf $(DESTDIR)$(LIBDIR)/libyosys.so
 ifeq ($(ENABLE_PYOSYS),1)
-	$(INSTALL_SUDO) rm -vf $(DESTDIR)$(PYTHON_DESTDIR)/$(subst -,_,$(PROGRAM_PREFIX))pyosys/libyosys.so
-	$(INSTALL_SUDO) rm -vf $(DESTDIR)$(PYTHON_DESTDIR)/$(subst -,_,$(PROGRAM_PREFIX))pyosys/__init__.py
-	$(INSTALL_SUDO) rmdir $(DESTDIR)$(PYTHON_DESTDIR)/$(subst -,_,$(PROGRAM_PREFIX))pyosys
+	$(INSTALL_SUDO) $(PYTHON_EXECUTABLE) -m pip uninstall -y pyosys
 endif
 endif
 
@@ -1005,13 +1024,13 @@ docs/source/cmd/abc.rst: $(TARGETS) $(EXTRA_TARGETS)
 	$(Q) mkdir -p docs/source/cmd
 	$(Q) mkdir -p temp/docs/source/cmd
 	$(Q) cd temp && ./../$(PROGRAM_PREFIX)yosys -p 'help -write-rst-command-reference-manual'
-	$(Q) rsync -rc temp/docs/source/cmd docs/source
+	$(Q) $(RSYNC_CP) temp/docs/source/cmd docs/source
 	$(Q) rm -rf temp
 docs/source/cell/word_add.rst: $(TARGETS) $(EXTRA_TARGETS)
 	$(Q) mkdir -p docs/source/cell
 	$(Q) mkdir -p temp/docs/source/cell
 	$(Q) cd temp && ./../$(PROGRAM_PREFIX)yosys -p 'help -write-rst-cells-manual'
-	$(Q) rsync -rc temp/docs/source/cell docs/source
+	$(Q) $(RSYNC_CP) temp/docs/source/cell docs/source
 	$(Q) rm -rf temp
 
 docs/source/generated/cells.json: docs/source/generated $(TARGETS) $(EXTRA_TARGETS)
@@ -1038,10 +1057,10 @@ docs/source/generated:
 
 # some commands return an error and print the usage text to stderr
 define DOC_USAGE_STDERR
-docs/source/generated/$(1): $(TARGETS) docs/source/generated
+docs/source/generated/$(1): $(TARGETS) docs/source/generated FORCE
 	-$(Q) ./$(PROGRAM_PREFIX)$(1) --help 2> $$@
 endef
-DOCS_USAGE_STDERR := yosys-config yosys-filterlib
+DOCS_USAGE_STDERR := yosys-filterlib
 
 # The in-tree ABC (yosys-abc) is only built when ABCEXTERNAL is not set.
 ifeq ($(ABCEXTERNAL),)
@@ -1053,9 +1072,9 @@ $(foreach usage,$(DOCS_USAGE_STDERR),$(eval $(call DOC_USAGE_STDERR,$(usage))))
 # others print to stdout
 define DOC_USAGE_STDOUT
 docs/source/generated/$(1): $(TARGETS) docs/source/generated
-	$(Q) ./$(PROGRAM_PREFIX)$(1) --help > $$@
+	$(Q) ./$(PROGRAM_PREFIX)$(1) --help > $$@ || rm $$@
 endef
-DOCS_USAGE_STDOUT := yosys yosys-smtbmc yosys-witness
+DOCS_USAGE_STDOUT := yosys yosys-smtbmc yosys-witness yosys-config
 $(foreach usage,$(DOCS_USAGE_STDOUT),$(eval $(call DOC_USAGE_STDOUT,$(usage))))
 
 docs/usage: $(addprefix docs/source/generated/,$(DOCS_USAGE_STDOUT) $(DOCS_USAGE_STDERR))
@@ -1075,6 +1094,7 @@ clean:
 	rm -rf kernel/*.pyh
 	rm -f $(OBJS) $(GENFILES) $(TARGETS) $(EXTRA_TARGETS) $(EXTRA_OBJS) $(PY_WRAP_INCLUDES) $(PY_WRAPPER_FILE).cc
 	rm -f kernel/version_*.o kernel/version_*.cc
+	rm -f kernel/python_wrappers.o
 	rm -f libs/*/*.d frontends/*/*.d passes/*/*.d backends/*/*.d kernel/*.d techlibs/*/*.d
 	rm -rf tests/asicworld/*.out tests/asicworld/*.log
 	rm -rf tests/hana/*.out tests/hana/*.log
@@ -1088,6 +1108,8 @@ clean:
 	rm -f $(addsuffix /run-test.mk,$(MK_TEST_DIRS))
 	-$(MAKE) -C docs clean
 	rm -rf docs/source/cmd docs/util/__pycache__
+	rm -f *.whl
+	rm -f libyosys.so
 
 clean-abc:
 	$(MAKE) -C abc DEP= clean
@@ -1190,5 +1212,7 @@ echo-cxx:
 -include kernel/*.d
 -include techlibs/*/*.d
 
+FORCE:
+
 .PHONY: all top-all abc test install install-abc docs clean mrproper qtcreator coverage vcxsrc
 .PHONY: config-clean config-clang config-gcc config-gcc-static config-gprof config-sudo

abc

@@ -1 +1 @@
-Subproject commit f2d68d590fa6f8fc32295a2edd79afc0d14a1414
+Subproject commit e55d316cc9a7f72a84a76eda555aa6ec083c9d0d

backends/aiger/xaiger.cc

@@ -53,6 +53,8 @@ struct XAigerWriter
 	dict<SigBit, float> arrival_times;
 
 	vector<pair<int, int>> aig_gates;
+	vector<SigBit> bit2aig_stack;
+	int next_loop_check = 1024;
 	vector<int> aig_outputs;
 	int aig_m = 0, aig_i = 0, aig_l = 0, aig_o = 0, aig_a = 0;
 
@@ -76,6 +78,24 @@ struct XAigerWriter
 			return it->second;
 		}
 
+		if (GetSize(bit2aig_stack)== next_loop_check) {
+			for (int i = 0; i < next_loop_check; ++i)
+			{
+				SigBit report_bit = bit2aig_stack[i];
+				if (report_bit != bit)
+					continue;
+				for (int j = i; j < next_loop_check; ++j) {
+					report_bit = bit2aig_stack[j];
+					if (report_bit.is_wire() && report_bit.wire->name.isPublic())
+						break;
+				}
+				log_error("Found combinatorial logic loop while processing signal %s.\n", log_signal(report_bit));
+			}
+			next_loop_check *= 2;
+		}
+
+		bit2aig_stack.push_back(bit);
+		
 		// NB: Cannot use iterator returned from aig_map.insert()
 		//     since this function is called recursively
 
@@ -93,6 +113,8 @@ struct XAigerWriter
 			a = bit2aig(alias_map.at(bit));
 		}
 
+		bit2aig_stack.pop_back();
+
 		if (bit == State::Sx || bit == State::Sz) {
 			log_debug("Design contains 'x' or 'z' bits. Treating as 1'b0.\n");
 			a = aig_map.at(State::S0);

backends/btor/btor.cc

@@ -30,6 +30,7 @@
 #include "kernel/mem.h"
 #include "kernel/json.h"
 #include "kernel/yw.h"
+#include "kernel/utils.h"
 #include <string>
 
 USING_YOSYS_NAMESPACE

backends/cxxrtl/cxxrtl_backend.cc

@@ -616,7 +616,7 @@ std::string escape_c_string(const std::string &input)
 				output.push_back('\\');
 			output.push_back(c);
 		} else {
-			char l = c & 0x3, m = (c >> 3) & 0x3, h = (c >> 6) & 0x3;
+			char l = c & 0x7, m = (c >> 3) & 0x7, h = (c >> 6) & 0x3;
 			output.append("\\");
 			output.push_back('0' + h);
 			output.push_back('0' + m);

backends/smt2/smt2.cc

@@ -24,6 +24,7 @@
 #include "kernel/log.h"
 #include "kernel/mem.h"
 #include "libs/json11/json11.hpp"
+#include "kernel/utils.h"
 #include <string>
 
 USING_YOSYS_NAMESPACE

docs/source/_images/Makefile

@@ -3,6 +3,12 @@ all: examples all_tex
 # set a fake time in pdf generation to prevent unnecessary differences in output
 FAKETIME := TZ='Z' faketime -f '2022-01-01 00:00:00 x0,001'
 
+ifneq ($(shell :; command -v rsync),)
+RSYNC_CP ?= rsync -t
+else
+RSYNC_CP ?= cp -a
+endif
+
 # find all code example makefiles
 .PHONY: examples
 CODE_EXAMPLES := ../code_examples/*/Makefile
@@ -19,7 +25,7 @@ FORCE:
 ../%/Makefile: FORCE
 	@make -C $(@D) dots
 	@mkdir -p $*
-	@find $(@D) -name *.dot -exec rsync -t {} $* \;
+	@find $(@D) -name *.dot -exec $(RSYNC_CP) {} $* \;
 
 # find and build all tex files
 .PHONY: all_tex

docs/source/cell/word_arith.rst

@@ -1,7 +1,7 @@
 Coarse arithmetics
 ------------------
 
-.. todo:: Add information about `$alu`, `$fa`, and `$lcu` cells.
+.. todo:: Add information about `$alu`, `$fa`, `$macc_v2`, and `$lcu` cells.
 
 The `$macc` cell type represents a generalized multiply and accumulate
 operation. The cell is purely combinational. It outputs the result of summing up

docs/source/code_examples/fifo/fifo.ys

@@ -67,7 +67,7 @@ show -color maroon3 @new_cells -notitle -format dot -prefix rdata_memrdv2 o:rdat
 # ========================================================
 
 alumacc
-select -set new_cells t:$alu t:$macc
+select -set new_cells t:$alu t:$macc_v2
 show -color maroon3 @new_cells -notitle -format dot -prefix rdata_alumacc o:rdata %ci*
 
 # ========================================================

docs/source/conf.py

@@ -6,7 +6,7 @@ import os
 project = 'YosysHQ Yosys'
 author = 'YosysHQ GmbH'
 copyright ='2025 YosysHQ GmbH'
-yosys_ver = "0.51"
+yosys_ver = "0.52"
 
 # select HTML theme
 html_theme = 'furo-ys'
@@ -16,15 +16,17 @@ html_theme_options: dict[str] = {
     "source_branch": "main",
     "source_directory": "docs/source/",
 }
+html_context: dict[str] = {}
 
 # try to fix the readthedocs detection
-html_context: dict[str] = {
-    "READTHEDOCS": True,
-    "display_github": True,
-    "github_user": "YosysHQ",
-    "github_repo": "yosys",
-    "slug": "yosys",
-}
+if os.getenv("READTHEDOCS"):
+    html_context.update({
+        "READTHEDOCS": True,
+        "display_github": True,
+        "github_user": "YosysHQ",
+        "github_repo": "yosys",
+        "slug": "yosys",
+    })
 
 # override source_branch if not main
 git_slug = os.getenv("READTHEDOCS_VERSION_NAME")
@@ -93,6 +95,9 @@ bibtex_bibfiles = ['literature.bib']
 latex_elements = {
         'releasename': 'Version',
         'preamble': r'''
+\pdfinfoomitdate 1
+\pdfsuppressptexinfo 1
+\pdftrailerid{}
 \usepackage{lmodern}
 \usepackage{comment}
 

docs/source/getting_started/example_synth.rst

@@ -523,7 +523,7 @@ That brings us to the fourth and final part for the iCE40 synthesis flow:
    :name: synth_coarse4
 
 Where before each type of arithmetic operation had its own cell, e.g. `$add`, we
-now want to extract these into `$alu` and `$macc` cells which can help identify
+now want to extract these into `$alu` and `$macc_v2` cells which can help identify
 opportunities for reusing logic.  We do this by running `alumacc`, which we can
 see produce the following changes in our example design:
 

docs/source/getting_started/installation.rst

@@ -34,31 +34,18 @@ Targeted architectures
 
 The `OSS CAD Suite`_ releases `nightly builds`_ for the following architectures:
 
-.. only:: html
+- **linux-x64** - Most personal Linux based computers
+- **darwin-x64** - macOS 12 or later with Intel CPU
+- **darwin-arm64** - macOS 12 or later with M1/M2 CPU
+- **windows-x64** - Targeted for Windows 10 and 11
+- **linux-arm64** - Devices such as Raspberry Pi with 64bit OS
 
-   - linux-x64 |linux-x64|
-      - Most personal Linux based computers
-
-   - darwin-x64 |darwin-x64|
-      - macOS 12 or later with Intel CPU
-
-   - darwin-arm64 |darwin-arm64|
-      - macOS 12 or later with M1/M2 CPU
-
-   - windows-x64 |windows-x64|
-      - Targeted for Windows 10 and 11
-
-   - linux-arm64 |linux-arm64|
+For more information about the targeted architectures, and the current build
+status, check the `OSS CAD Suite`_ git repository.
 
 .. _OSS CAD Suite: https://github.com/YosysHQ/oss-cad-suite-build
 .. _nightly builds: https://github.com/YosysHQ/oss-cad-suite-build/releases/latest
 
-.. |linux-x64| image:: https://github.com/YosysHQ/oss-cad-suite-build/actions/workflows/linux-x64.yml/badge.svg
-.. |darwin-x64| image:: https://github.com/YosysHQ/oss-cad-suite-build/actions/workflows/darwin-x64.yml/badge.svg
-.. |darwin-arm64| image:: https://github.com/YosysHQ/oss-cad-suite-build/actions/workflows/darwin-arm64.yml/badge.svg
-.. |windows-x64| image:: https://github.com/YosysHQ/oss-cad-suite-build/actions/workflows/windows-x64.yml/badge.svg
-.. |linux-arm64| image:: https://github.com/YosysHQ/oss-cad-suite-build/actions/workflows/linux-arm64.yml/badge.svg
-
 Building from source
 ~~~~~~~~~~~~~~~~~~~~
 

docs/source/yosys_internals/extending_yosys/test_suites.rst

@@ -6,22 +6,12 @@ Testing Yosys
 Automatic testing
 -----------------
 
-.. only:: html
-
-   The `Yosys Git repo`_ has automatic testing of builds and running of the
-   included test suite on the following platforms:
-
-   - Ubuntu |test-linux|
-   - macOS |test-macos|
+The `Yosys Git repo`_ has automatic testing of builds and running of the
+included test suite on both Ubuntu and macOS, as well as across range of
+compiler versions.  For up to date information, including OS versions, refer to
+`the git actions page`_.
 
 .. _Yosys Git repo: https://github.com/YosysHQ/yosys
-
-.. |test-linux| image:: https://github.com/YosysHQ/yosys/actions/workflows/test-linux.yml/badge.svg?branch=main
-.. |test-macos| image:: https://github.com/YosysHQ/yosys/actions/workflows/test-macos.yml/badge.svg?branch=main
-
-For up to date information, including OS versions, refer to `the git actions
-page`_.
-
 .. _the git actions page: https://github.com/YosysHQ/yosys/actions
 
 .. todo:: are unit tests currently working

frontends/liberty/liberty.cc

@@ -539,7 +539,7 @@ struct LibertyFrontend : public Frontend {
 
 		log_header(design, "Executing Liberty frontend: %s\n", filename.c_str());
 
-		LibertyParser parser(*f);
+		LibertyParser parser(*f, filename);
 		int cell_count = 0;
 
 		std::map<std::string, std::tuple<int, int, bool>> global_type_map;

frontends/verific/verific.cc

@@ -21,6 +21,7 @@
 #include "kernel/sigtools.h"
 #include "kernel/celltypes.h"
 #include "kernel/log.h"
+#include "kernel/utils.h"
 #include "libs/sha1/sha1.h"
 #include <stdlib.h>
 #include <stdio.h>
@@ -3402,6 +3403,7 @@ struct VerificPass : public Pass {
 				veri_module->SetCompileAsBlackbox();
 			}
 		}
+		restore_blackbox_msg_state();
 	}
 #endif
 
@@ -4298,7 +4300,7 @@ struct ReadPass : public Pass {
 		log("\n");
 		log("    read {-f|-F} <command-file>\n");
 		log("\n");
-		log("Load and execute the specified command file. (Requires Verific.)\n");
+		log("Load and execute the specified command file.\n");
 		log("Check verific command for more information about supported commands in file.\n");
 		log("\n");
 		log("\n");
@@ -4412,10 +4414,14 @@ struct ReadPass : public Pass {
 		if (args[1] == "-f" || args[1] == "-F") {
 			if (use_verific) {
 				args[0] = "verific";
-				Pass::call(design, args);
 			} else {
-				cmd_error(args, 1, "This version of Yosys is built without Verific support.\n");
+#if !defined(__wasm)
+				args[0] = "read_verilog_file_list";
+#else
+				cmd_error(args, 1, "Command files are not supported on this platform.\n");
+#endif
 			}
+			Pass::call(design, args);
 			return;
 		}
 

frontends/verilog/verilog_frontend.cc

@@ -26,6 +26,10 @@
  *
  */
 
+#if !defined(__wasm)
+#include <filesystem>
+#endif
+
 #include "verilog_frontend.h"
 #include "preproc.h"
 #include "kernel/yosys.h"
@@ -672,6 +676,89 @@ struct VerilogDefines : public Pass {
 	}
 } VerilogDefines;
 
+#if !defined(__wasm)
+
+static void parse_file_list(const std::string &file_list_path, RTLIL::Design *design, bool relative_to_file_list_path)
+{
+	std::ifstream flist(file_list_path);
+	if (!flist.is_open()) {
+		log_error("Verilog file list file does not exist");
+		exit(1);
+	}
+
+	std::filesystem::path file_list_parent_dir = std::filesystem::path(file_list_path).parent_path();
+
+	std::string v_file_name;
+	while (std::getline(flist, v_file_name)) {
+		if (v_file_name.empty()) {
+			continue;
+		}
+
+		std::filesystem::path verilog_file_path;
+		if (relative_to_file_list_path) {
+			verilog_file_path = file_list_parent_dir / v_file_name;
+		} else {
+			verilog_file_path = std::filesystem::current_path() / v_file_name;
+		}
+
+		bool is_sv = (verilog_file_path.extension() == ".sv");
+
+		std::vector<std::string> read_verilog_cmd = {"read_verilog", "-defer"};
+		if (is_sv) {
+			read_verilog_cmd.push_back("-sv");
+		}
+		read_verilog_cmd.push_back(verilog_file_path.string());
+		Pass::call(design, read_verilog_cmd);
+	}
+
+	flist.close();
+}
+
+struct VerilogFileList : public Pass {
+	VerilogFileList() : Pass("read_verilog_file_list", "parse a Verilog file list") {}
+	void help() override
+	{
+		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+		log("\n");
+		log("    read_verilog_file_list [options]\n");
+		log("\n");
+		log("Parse a Verilog file list, and pass the list of Verilog files to read_verilog\n");
+		log("command\n");
+		log("\n");
+		log("    -F file_list_path\n");
+		log("        File list file contains list of Verilog files to be parsed, any path is\n");
+		log("        treated relative to the file list file\n");
+		log("\n");
+		log("    -f file_list_path\n");
+		log("        File list file contains list of Verilog files to be parsed, any path is\n");
+		log("        treated relative to current working directroy\n");
+		log("\n");
+	}
+
+	void execute(std::vector<std::string> args, RTLIL::Design *design) override
+	{
+		size_t argidx;
+		for (argidx = 1; argidx < args.size(); argidx++) {
+			std::string arg = args[argidx];
+			if (arg == "-F" && argidx + 1 < args.size()) {
+				std::string file_list_path = args[++argidx];
+				parse_file_list(file_list_path, design, true);
+				continue;
+			}
+			if (arg == "-f" && argidx + 1 < args.size()) {
+				std::string file_list_path = args[++argidx];
+				parse_file_list(file_list_path, design, false);
+				continue;
+			}
+			break;
+		}
+
+		extra_args(args, argidx, design);
+	}
+} VerilogFilelist;
+
+#endif
+
 YOSYS_NAMESPACE_END
 
 // the yyerror function used by bison to report parser errors

kernel/celledges.cc

@@ -453,7 +453,7 @@ bool YOSYS_NAMESPACE_PREFIX AbstractCellEdgesDatabase::add_edges_from_cell(RTLIL
 	}
 
 	// FIXME: $mul $div $mod $divfloor $modfloor $slice $concat
-	// FIXME: $lut $sop $alu $lcu $macc $fa
+	// FIXME: $lut $sop $alu $lcu $macc $macc_v2 $fa
 	// FIXME: $mul $div $mod $divfloor $modfloor $pow $slice $concat $bweqx
 	// FIXME: $lut $sop $alu $lcu $macc $fa $logic_and $logic_or $bwmux
 

kernel/celltypes.h

@@ -144,6 +144,7 @@ struct CellTypes
 
 		setup_type(ID($lcu), {ID::P, ID::G, ID::CI}, {ID::CO}, true);
 		setup_type(ID($alu), {ID::A, ID::B, ID::CI, ID::BI}, {ID::X, ID::Y, ID::CO}, true);
+		setup_type(ID($macc_v2), {ID::A, ID::B, ID::C}, {ID::Y}, true);
 		setup_type(ID($fa), {ID::A, ID::B, ID::C}, {ID::X, ID::Y}, true);
 	}
 

kernel/consteval.h

@@ -310,7 +310,7 @@ struct ConstEval
 				}
 			}
 		}
-		else if (cell->type == ID($macc))
+		else if (cell->type.in(ID($macc), ID($macc_v2)))
 		{
 			Macc macc;
 			macc.from_cell(cell);

kernel/constids.inc

@@ -276,3 +276,11 @@ X(Y)
 X(Y_WIDTH)
 X(area)
 X(capacitance)
+X(NPRODUCTS)
+X(NADDENDS)
+X(PRODUCT_NEGATED)
+X(ADDEND_NEGATED)
+X(A_WIDTHS)
+X(B_WIDTHS)
+X(C_WIDTHS)
+X(C_SIGNED)

kernel/fmt.cc

@@ -634,10 +634,11 @@ std::string escape_cxx_string(const std::string &input)
 				output.push_back('\\');
 			output.push_back(c);
 		} else {
-			char l = c & 0xf, h = (c >> 4) & 0xf;
-			output.append("\\x");
-			output.push_back((h < 10 ? '0' + h : 'a' + h - 10));
-			output.push_back((l < 10 ? '0' + l : 'a' + l - 10));
+			char l = c & 0x7, m = (c >> 3) & 0x7, h = (c >> 6) & 0x3;
+			output.push_back('\\');
+			output.push_back('0' + h);
+			output.push_back('0' + m);
+			output.push_back('0' + l);
 		}
 	}
 	output.push_back('"');

kernel/gzip.cc

@@ -0,0 +1,139 @@
+#include "kernel/yosys_common.h"
+#include "kernel/log.h"
+#include "kernel/gzip.h"
+#include <iostream>
+#include <string>
+#include <cstdarg>
+#include <cstdio>
+
+#if !defined(WIN32)
+#include <dirent.h>
+#include <unistd.h>
+#else
+#include <io.h>
+#endif
+
+YOSYS_NAMESPACE_BEGIN
+
+#ifdef YOSYS_ENABLE_ZLIB
+
+gzip_ostream::obuf::obuf() {
+    setp(buffer, buffer + buffer_size - 1);
+}
+
+bool gzip_ostream::obuf::open(const std::string &filename) {
+    gzf = Zlib::gzopen(filename.c_str(), "wb");
+    return gzf != nullptr;
+}
+
+int gzip_ostream::obuf::sync() {
+    int num = pptr() - pbase();
+    if (num > 0) {
+        if (Zlib::gzwrite(gzf, reinterpret_cast<const void*>(pbase()), num) != num) {
+            return -1;
+        }
+        pbump(-num);
+    }
+    return 0;
+}
+
+gzip_ostream::obuf::~obuf() {
+    if (gzf) {
+        sync();
+        Zlib::gzclose(gzf);
+    }
+}
+
+bool gzip_istream::ibuf::open(const std::string& filename) {
+	if (gzf) {
+		Zlib::gzclose(gzf);
+	}
+	gzf = Zlib::gzopen(filename.c_str(), "rb");
+	if (!gzf) {
+		return false;
+	}
+	// Empty and point to start
+	setg(buffer, buffer, buffer);
+	return true;
+}
+
+// Called when the buffer is empty and more input is needed
+std::istream::int_type gzip_istream::ibuf::underflow() {
+	log_assert(gzf && "No gzfile opened\n");
+	int bytes_read = Zlib::gzread(gzf, buffer, buffer_size);
+	if (bytes_read <= 0) {
+		if (Zlib::gzeof(gzf)) {
+			// "On failure, the function ensures that either
+			// gptr() == nullptr or gptr() == egptr."
+			// Let's set gptr to egptr
+			setg(eback(), egptr(), egptr());
+			return traits_type::eof();
+		}
+
+		int err;
+		const char* error_msg = Zlib::gzerror(gzf, &err);
+		if (err != Z_OK)
+			log_error("%s", error_msg);
+		else
+			log_error("Decompression logic failure: "\
+					"read <=0 bytes but neither EOF nor error\n");
+	}
+
+	// Keep size and point to start
+	setg(buffer, buffer, buffer + bytes_read);
+	return traits_type::to_int_type(buffer[0]);
+}
+
+gzip_istream::ibuf::~ibuf() {
+	if (gzf) {
+		int err = Zlib::gzclose(gzf);
+		if (err != Z_OK) {
+			// OK to overwrite rr it, it doesn't change
+			const char* error_msg = Zlib::gzerror(gzf, &err);
+			log_error("%s", error_msg);
+		}
+	}
+}
+
+#endif // YOSYS_ENABLE_ZLIB
+
+
+// Takes a successfully opened ifstream. If it's gzipped, returns an istream. Otherwise,
+// returns the original ifstream, rewound to the start.
+std::istream* uncompressed(const std::string filename, std::ios_base::openmode mode) {
+	std::ifstream* f = new std::ifstream();
+	f->open(filename, mode);
+	if (f->fail())
+		return f;
+	// Check for gzip magic
+	unsigned char magic[3];
+	int n = 0;
+	while (n < 3)
+	{
+		int c = f->get();
+		if (c != EOF) {
+			magic[n] = (unsigned char) c;
+		}
+		n++;
+	}
+	if (n == 3 && magic[0] == 0x1f && magic[1] == 0x8b) {
+#ifdef YOSYS_ENABLE_ZLIB
+		log("Found gzip magic in file `%s', decompressing using zlib.\n", filename.c_str());
+		if (magic[2] != 8)
+			log_cmd_error("gzip file `%s' uses unsupported compression type %02x\n",
+				filename.c_str(), unsigned(magic[2]));
+		gzip_istream* s = new gzip_istream();
+		delete f;
+		s->open(filename.c_str());
+		return s;
+#else
+		log_cmd_error("File `%s' is a gzip file, but Yosys is compiled without zlib.\n", filename.c_str());
+#endif // YOSYS_ENABLE_ZLIB
+	} else {
+		f->clear();
+		f->seekg(0, std::ios::beg);
+		return f;
+	}
+}
+
+YOSYS_NAMESPACE_END

kernel/gzip.h

@@ -0,0 +1,78 @@
+#include <string>
+#include "kernel/yosys_common.h"
+
+#ifndef YOSYS_GZIP_H
+#define YOSYS_GZIP_H
+
+YOSYS_NAMESPACE_BEGIN
+
+#ifdef YOSYS_ENABLE_ZLIB
+
+namespace Zlib {
+#include <zlib.h>
+}
+
+/*
+An output stream that uses a stringbuf to buffer data internally,
+using zlib to write gzip-compressed data every time the stream is flushed.
+*/
+class gzip_ostream : public std::ostream {
+public:
+	gzip_ostream(): std::ostream(nullptr) {
+		rdbuf(&outbuf);
+	}
+	bool open(const std::string &filename) {
+		return outbuf.open(filename);
+	}
+private:
+	class obuf : public std::stringbuf {
+	public:
+		obuf();
+		bool open(const std::string &filename);
+		virtual int sync() override;
+		virtual ~obuf();
+	private:
+		static const int buffer_size = 4096;
+		char buffer[buffer_size];             // Internal buffer for compressed data
+		Zlib::gzFile gzf = nullptr;                 // Handle to the gzip file
+	};
+
+	obuf outbuf;  // The stream buffer instance
+};
+
+/*
+An input stream that uses zlib to read gzip-compressed data from a file,
+buffering the decompressed data internally using its own buffer.
+*/
+class gzip_istream final : public std::istream {
+public:
+	gzip_istream() : std::istream(&inbuf) {}
+	bool open(const std::string& filename) {
+		return inbuf.open(filename);
+	}
+private:
+	class ibuf final : public std::streambuf {
+	public:
+		ibuf() : gzf(nullptr) {}
+		bool open(const std::string& filename);
+		virtual ~ibuf();
+
+	protected:
+		// Called when the buffer is empty and more input is needed
+		virtual int_type underflow() override;
+	private:
+		static const int buffer_size = 8192;
+		char buffer[buffer_size];
+		Zlib::gzFile gzf;
+	};
+
+	ibuf inbuf;  // The stream buffer instance
+};
+
+#endif // YOSYS_ENABLE_ZLIB
+
+std::istream* uncompressed(const std::string filename, std::ios_base::openmode mode = std::ios_base::in);
+
+YOSYS_NAMESPACE_END
+
+#endif // YOSYS_GZIP_H

kernel/io.cc

@@ -0,0 +1,370 @@
+#include "kernel/yosys_common.h"
+#include "kernel/log.h"
+#include <iostream>
+#include <string>
+
+#if !defined(WIN32)
+#include <dirent.h>
+#include <unistd.h>
+#else
+#include <io.h>
+#endif
+
+YOSYS_NAMESPACE_BEGIN
+
+// Set of utilities for handling files
+
+int readsome(std::istream &f, char *s, int n)
+{
+	int rc = int(f.readsome(s, n));
+
+	// f.readsome() sometimes returns 0 on a non-empty stream..
+	if (rc == 0) {
+		int c = f.get();
+		if (c != EOF) {
+			*s = c;
+			rc = 1;
+		}
+	}
+
+	return rc;
+}
+
+std::string next_token(std::string &text, const char *sep, bool long_strings)
+{
+	size_t pos_begin = text.find_first_not_of(sep);
+
+	if (pos_begin == std::string::npos)
+		pos_begin = text.size();
+
+	if (long_strings && pos_begin != text.size() && text[pos_begin] == '"') {
+		std::string sep_string = sep;
+		for (size_t i = pos_begin+1; i < text.size(); i++) {
+			if (text[i] == '"' && (i+1 == text.size() || sep_string.find(text[i+1]) != std::string::npos)) {
+				std::string token = text.substr(pos_begin, i-pos_begin+1);
+				text = text.substr(i+1);
+				return token;
+			}
+			if (i+1 < text.size() && text[i] == '"' && text[i+1] == ';' && (i+2 == text.size() || sep_string.find(text[i+2]) != std::string::npos)) {
+				std::string token = text.substr(pos_begin, i-pos_begin+1);
+				text = text.substr(i+2);
+				return token + ";";
+			}
+		}
+	}
+
+	size_t pos_end = text.find_first_of(sep, pos_begin);
+
+	if (pos_end == std::string::npos)
+		pos_end = text.size();
+
+	std::string token = text.substr(pos_begin, pos_end-pos_begin);
+	text = text.substr(pos_end);
+	return token;
+}
+
+std::vector<std::string> split_tokens(const std::string &text, const char *sep)
+{
+	std::vector<std::string> tokens;
+	std::string current_token;
+	for (char c : text) {
+		if (strchr(sep, c)) {
+			if (!current_token.empty()) {
+				tokens.push_back(current_token);
+				current_token.clear();
+			}
+		} else
+			current_token += c;
+	}
+	if (!current_token.empty()) {
+		tokens.push_back(current_token);
+		current_token.clear();
+	}
+	return tokens;
+}
+
+// this is very similar to fnmatch(). the exact rules used by this
+// function are:
+//
+//    ?        matches any character except
+//    *        matches any sequence of characters
+//    [...]    matches any of the characters in the list
+//    [!..]    matches any of the characters not in the list
+//
+// a backslash may be used to escape the next characters in the
+// pattern. each special character can also simply match itself.
+//
+bool patmatch(const char *pattern, const char *string)
+{
+	if (*pattern == 0)
+		return *string == 0;
+
+	if (*pattern == '\\') {
+		if (pattern[1] == string[0] && patmatch(pattern+2, string+1))
+			return true;
+	}
+
+	if (*pattern == '?') {
+		if (*string == 0)
+			return false;
+		return patmatch(pattern+1, string+1);
+	}
+
+	if (*pattern == '*') {
+		while (*string) {
+			if (patmatch(pattern+1, string++))
+				return true;
+		}
+		return pattern[1] == 0;
+	}
+
+	if (*pattern == '[') {
+		bool found_match = false;
+		bool inverted_list = pattern[1] == '!';
+		const char *p = pattern + (inverted_list ? 1 : 0);
+
+		while (*++p) {
+			if (*p == ']') {
+				if (found_match != inverted_list && patmatch(p+1, string+1))
+					return true;
+				break;
+			}
+
+			if (*p == '\\') {
+				if (*++p == *string)
+					found_match = true;
+			} else
+			if (*p == *string)
+				found_match = true;
+		}
+	}
+
+	if (*pattern == *string)
+		return patmatch(pattern+1, string+1);
+
+	return false;
+}
+
+std::string get_base_tmpdir()
+{
+	static std::string tmpdir;
+
+	if (!tmpdir.empty()) {
+		return tmpdir;
+	}
+
+#if defined(_WIN32)
+#  ifdef __MINGW32__
+	char longpath[MAX_PATH + 1];
+	char shortpath[MAX_PATH + 1];
+#  else
+	WCHAR longpath[MAX_PATH + 1];
+	TCHAR shortpath[MAX_PATH + 1];
+#  endif
+	if (!GetTempPath(MAX_PATH+1, longpath))
+		log_error("GetTempPath() failed.\n");
+	if (!GetShortPathName(longpath, shortpath, MAX_PATH + 1))
+		log_error("GetShortPathName() failed.\n");
+	for (int i = 0; shortpath[i]; i++)
+		tmpdir += char(shortpath[i]);
+#else
+	char * var = std::getenv("TMPDIR");
+	if (var && strlen(var)!=0) {
+		tmpdir.assign(var);
+		// We return the directory name without the trailing '/'
+		while (!tmpdir.empty() && (tmpdir.back() == '/')) {
+			tmpdir.pop_back();
+		}
+	} else {
+		tmpdir.assign("/tmp");
+	}
+#endif
+	return tmpdir;
+}
+
+std::string make_temp_file(std::string template_str)
+{
+	size_t pos = template_str.rfind("XXXXXX");
+	log_assert(pos != std::string::npos);
+#if defined(__wasm)
+	static size_t index = 0;
+	template_str.replace(pos, 6, stringf("%06zu", index++));
+#elif defined(_WIN32)
+#ifndef YOSYS_WIN32_UNIX_DIR
+	std::replace(template_str.begin(), template_str.end(), '/', '\\');
+#endif
+	while (1) {
+		for (int i = 0; i < 6; i++) {
+			static std::string y = "0123456789abcdefghijklmnopqrstuvwxyzABCDEFGHIJKLMNOPQRSTUVWXYZ";
+			static uint32_t x = 314159265 ^ uint32_t(time(NULL));
+			x ^= x << 13, x ^= x >> 17, x ^= x << 5;
+			template_str[pos+i] = y[x % y.size()];
+		}
+		if (_access(template_str.c_str(), 0) != 0)
+			break;
+	}
+#else
+	int suffixlen = template_str.size() - pos - 6;
+
+	char *p = strdup(template_str.c_str());
+	close(mkstemps(p, suffixlen));
+	template_str = p;
+	free(p);
+#endif
+
+	return template_str;
+}
+
+std::string make_temp_dir(std::string template_str)
+{
+#if defined(_WIN32)
+	template_str = make_temp_file(template_str);
+	mkdir(template_str.c_str());
+	return template_str;
+#elif defined(__wasm)
+	template_str = make_temp_file(template_str);
+	mkdir(template_str.c_str(), 0777);
+	return template_str;
+#else
+#  ifndef NDEBUG
+	size_t pos = template_str.rfind("XXXXXX");
+	log_assert(pos != std::string::npos);
+
+	int suffixlen = template_str.size() - pos - 6;
+	log_assert(suffixlen == 0);
+#  endif
+
+	char *p = strdup(template_str.c_str());
+	log_assert(p);
+	char *res = mkdtemp(p);
+	if (!res)
+		log_error("mkdtemp failed for '%s': %s [Error %d]\n",
+			p, strerror(errno), errno);
+	template_str = p;
+	free(p);
+
+	return template_str;
+#endif
+}
+
+bool check_directory_exists(const std::string& dirname)
+{
+#if defined(_WIN32)
+	struct _stat info;
+	if (_stat(dirname.c_str(), &info) != 0)
+	{
+		return false;
+	}
+	return (info.st_mode & _S_IFDIR) != 0;
+#else
+	struct stat info;
+	if (stat(dirname.c_str(), &info) != 0)
+	{
+		return false;
+	}
+	return (info.st_mode & S_IFDIR) != 0;
+#endif
+}
+
+#ifdef _WIN32
+bool check_file_exists(std::string filename, bool)
+{
+	return _access(filename.c_str(), 0) == 0;
+}
+#else
+bool check_file_exists(std::string filename, bool is_exec)
+{
+	return access(filename.c_str(), is_exec ? X_OK : F_OK) == 0;
+}
+#endif
+
+bool is_absolute_path(std::string filename)
+{
+#ifdef _WIN32
+	return filename[0] == '/' || filename[0] == '\\' || (filename[0] != 0 && filename[1] == ':');
+#else
+	return filename[0] == '/';
+#endif
+}
+
+void remove_directory(std::string dirname)
+{
+#ifdef _WIN32
+	run_command(stringf("rmdir /s /q \"%s\"", dirname.c_str()));
+#else
+	struct stat stbuf;
+	struct dirent **namelist;
+	int n = scandir(dirname.c_str(), &namelist, nullptr, alphasort);
+	log_assert(n >= 0);
+	for (int i = 0; i < n; i++) {
+		if (strcmp(namelist[i]->d_name, ".") && strcmp(namelist[i]->d_name, "..")) {
+			std::string buffer = stringf("%s/%s", dirname.c_str(), namelist[i]->d_name);
+			if (!stat(buffer.c_str(), &stbuf) && S_ISREG(stbuf.st_mode)) {
+				remove(buffer.c_str());
+			} else
+				remove_directory(buffer);
+		}
+		free(namelist[i]);
+	}
+	free(namelist);
+	rmdir(dirname.c_str());
+#endif
+}
+
+bool create_directory(const std::string& dirname)
+{
+#if defined(_WIN32)
+	int ret = _mkdir(dirname.c_str());
+#else
+	mode_t mode = 0755;
+	int ret = mkdir(dirname.c_str(), mode);
+#endif
+	if (ret == 0)
+		return true;
+
+	switch (errno)
+	{
+	case ENOENT:
+		// parent didn't exist, try to create it
+		{
+			std::string::size_type pos = dirname.find_last_of('/');
+			if (pos == std::string::npos)
+#if defined(_WIN32)
+				pos = dirname.find_last_of('\\');
+			if (pos == std::string::npos)
+#endif
+				return false;
+			if (!create_directory( dirname.substr(0, pos) ))
+				return false;
+		}
+		// now, try to create again
+#if defined(_WIN32)
+		return 0 == _mkdir(dirname.c_str());
+#else
+		return 0 == mkdir(dirname.c_str(), mode);
+#endif
+
+	case EEXIST:
+		// done!
+		return check_directory_exists(dirname);
+
+	default:
+		return false;
+	}
+}
+
+std::string escape_filename_spaces(const std::string& filename)
+{
+	std::string out;
+	out.reserve(filename.size());
+	for (auto c : filename)
+	{
+		if (c == ' ')
+			out += "\\ ";
+		else
+			out.push_back(c);
+	}
+	return out;
+}
+
+YOSYS_NAMESPACE_END

kernel/io.h

@@ -0,0 +1,69 @@
+#include <string>
+#include <stdarg.h>
+#include "kernel/yosys_common.h"
+
+#ifndef YOSYS_IO_H
+#define YOSYS_IO_H
+
+YOSYS_NAMESPACE_BEGIN
+
+inline std::string vstringf(const char *fmt, va_list ap)
+{
+	// For the common case of strings shorter than 128, save a heap
+	// allocation by using a stack allocated buffer.
+	const int kBufSize = 128;
+	char buf[kBufSize];
+	buf[0] = '\0';
+	va_list apc;
+	va_copy(apc, ap);
+	int n = vsnprintf(buf, kBufSize, fmt, apc);
+	va_end(apc);
+	if (n < kBufSize)
+		return std::string(buf);
+
+	std::string string;
+	char *str = NULL;
+#if defined(_WIN32) || defined(__CYGWIN__)
+	int sz = 2 * kBufSize, rc;
+	while (1) {
+		va_copy(apc, ap);
+		str = (char *)realloc(str, sz);
+		rc = vsnprintf(str, sz, fmt, apc);
+		va_end(apc);
+		if (rc >= 0 && rc < sz)
+			break;
+		sz *= 2;
+	}
+	if (str != NULL) {
+		string = str;
+		free(str);
+	}
+	return string;
+#else
+	if (vasprintf(&str, fmt, ap) < 0)
+		str = NULL;
+	if (str != NULL) {
+		string = str;
+		free(str);
+	}
+	return string;
+#endif
+}
+
+std::string stringf(const char *fmt, ...) YS_ATTRIBUTE(format(printf, 1, 2));
+
+inline std::string stringf(const char *fmt, ...)
+{
+	std::string string;
+	va_list ap;
+
+	va_start(ap, fmt);
+	string = vstringf(fmt, ap);
+	va_end(ap);
+
+	return string;
+}
+
+YOSYS_NAMESPACE_END
+
+#endif // YOSYS_IO_H

kernel/macc.h

@@ -82,7 +82,7 @@ struct Macc
 		new_ports.swap(ports);
 	}
 
-	void from_cell(RTLIL::Cell *cell)
+	void from_cell_v1(RTLIL::Cell *cell)
 	{
 		RTLIL::SigSpec port_a = cell->getPort(ID::A);
 
@@ -136,52 +136,128 @@ struct Macc
 		log_assert(port_a_cursor == GetSize(port_a));
 	}
 
-	void to_cell(RTLIL::Cell *cell) const
+	void from_cell(RTLIL::Cell *cell)
 	{
-		RTLIL::SigSpec port_a;
-		std::vector<RTLIL::State> config_bits;
-		int max_size = 0, num_bits = 0;
+		if (cell->type == ID($macc)) {
+			from_cell_v1(cell);
+			return;
+		}
+		log_assert(cell->type == ID($macc_v2));
 
-		for (auto &port : ports) {
-			max_size = max(max_size, GetSize(port.in_a));
-			max_size = max(max_size, GetSize(port.in_b));
+		RTLIL::SigSpec port_a = cell->getPort(ID::A);
+		RTLIL::SigSpec port_b = cell->getPort(ID::B);
+		RTLIL::SigSpec port_c = cell->getPort(ID::C);
+
+		ports.clear();
+
+		int nproducts = cell->getParam(ID::NPRODUCTS).as_int();
+		const Const &product_neg = cell->getParam(ID::PRODUCT_NEGATED);
+		const Const &a_widths = cell->getParam(ID::A_WIDTHS);
+		const Const &b_widths = cell->getParam(ID::B_WIDTHS);
+		const Const &a_signed = cell->getParam(ID::A_SIGNED);
+		const Const &b_signed = cell->getParam(ID::B_SIGNED);
+		int ai = 0, bi = 0;
+		for (int i = 0; i < nproducts; i++) {
+			port_t term;
+
+			log_assert(a_signed[i] == b_signed[i]);
+			term.is_signed = (a_signed[i] == State::S1);
+			int a_width = a_widths.extract(16 * i, 16).as_int(false);
+			int b_width = b_widths.extract(16 * i, 16).as_int(false);
+
+			term.in_a = port_a.extract(ai, a_width);
+			ai += a_width;
+			term.in_b = port_b.extract(bi, b_width);
+			bi += b_width;
+			term.do_subtract = (product_neg[i] == State::S1);
+
+			ports.push_back(term);
+		}
+		log_assert(port_a.size() == ai);
+		log_assert(port_b.size() == bi);
+
+		int naddends = cell->getParam(ID::NADDENDS).as_int();
+		const Const &addend_neg = cell->getParam(ID::ADDEND_NEGATED);
+		const Const &c_widths = cell->getParam(ID::C_WIDTHS);
+		const Const &c_signed = cell->getParam(ID::C_SIGNED);
+		int ci = 0;
+		for (int i = 0; i < naddends; i++) {
+			port_t term;
+
+			term.is_signed = (c_signed[i] == State::S1);
+			int c_width = c_widths.extract(16 * i, 16).as_int(false);
+
+			term.in_a = port_c.extract(ci, c_width);
+			ci += c_width;
+			term.do_subtract = (addend_neg[i] == State::S1);
+
+			ports.push_back(term);
+		}
+		log_assert(port_c.size() == ci);
+	}
+
+	void to_cell(RTLIL::Cell *cell)
+	{
+		cell->type = ID($macc_v2);
+
+		int nproducts = 0, naddends = 0;
+		Const a_signed, b_signed, a_widths, b_widths, product_negated;
+		Const c_signed, c_widths, addend_negated;
+		SigSpec a, b, c;
+
+		for (int i = 0; i < (int) ports.size(); i++) {
+			SigSpec term_a = ports[i].in_a, term_b = ports[i].in_b;
+
+			if (term_b.empty()) {
+				// addend
+				c_widths.append(Const(term_a.size(), 16));
+				c_signed.append(ports[i].is_signed ? RTLIL::S1 : RTLIL::S0);
+				addend_negated.append(ports[i].do_subtract ? RTLIL::S1 : RTLIL::S0);
+				c.append(term_a);
+				naddends++;
+			} else {
+				// product
+				a_widths.append(Const(term_a.size(), 16));
+				b_widths.append(Const(term_b.size(), 16));
+				a_signed.append(ports[i].is_signed ? RTLIL::S1 : RTLIL::S0);
+				b_signed.append(ports[i].is_signed ? RTLIL::S1 : RTLIL::S0);
+				product_negated.append(ports[i].do_subtract ? RTLIL::S1 : RTLIL::S0);
+				a.append(term_a);
+				b.append(term_b);
+				nproducts++;
+			}
 		}
 
-		while (max_size)
-			num_bits++, max_size /= 2;
+		if (a_signed.empty())
+			a_signed = {RTLIL::Sx};
+		if (b_signed.empty())
+			b_signed = {RTLIL::Sx};
+		if (c_signed.empty())
+			c_signed = {RTLIL::Sx};
+		if (a_widths.empty())
+			a_widths = {RTLIL::Sx};
+		if (b_widths.empty())
+			b_widths = {RTLIL::Sx};
+		if (c_widths.empty())
+			c_widths = {RTLIL::Sx};
+		if (product_negated.empty())
+			product_negated = {RTLIL::Sx};
+		if (addend_negated.empty())
+			addend_negated = {RTLIL::Sx};
 
-		log_assert(num_bits < 16);
-		config_bits.push_back(num_bits & 1 ? State::S1 : State::S0);
-		config_bits.push_back(num_bits & 2 ? State::S1 : State::S0);
-		config_bits.push_back(num_bits & 4 ? State::S1 : State::S0);
-		config_bits.push_back(num_bits & 8 ? State::S1 : State::S0);
-
-		for (auto &port : ports)
-		{
-			if (GetSize(port.in_a) == 0)
-				continue;
-
-			config_bits.push_back(port.is_signed ? State::S1 : State::S0);
-			config_bits.push_back(port.do_subtract ? State::S1 : State::S0);
-
-			int size_a = GetSize(port.in_a);
-			for (int i = 0; i < num_bits; i++)
-				config_bits.push_back(size_a & (1 << i) ? State::S1 : State::S0);
-
-			int size_b = GetSize(port.in_b);
-			for (int i = 0; i < num_bits; i++)
-				config_bits.push_back(size_b & (1 << i) ? State::S1 : State::S0);
-
-			port_a.append(port.in_a);
-			port_a.append(port.in_b);
-		}
-
-		cell->setPort(ID::A, port_a);
-		cell->setPort(ID::B, {});
-		cell->setParam(ID::CONFIG, config_bits);
-		cell->setParam(ID::CONFIG_WIDTH, GetSize(config_bits));
-		cell->setParam(ID::A_WIDTH, GetSize(port_a));
-		cell->setParam(ID::B_WIDTH, 0);
+		cell->setParam(ID::NPRODUCTS, nproducts);
+		cell->setParam(ID::PRODUCT_NEGATED, product_negated);
+		cell->setParam(ID::NADDENDS, naddends);
+		cell->setParam(ID::ADDEND_NEGATED, addend_negated);
+		cell->setParam(ID::A_SIGNED, a_signed);
+		cell->setParam(ID::B_SIGNED, b_signed);
+		cell->setParam(ID::C_SIGNED, c_signed);
+		cell->setParam(ID::A_WIDTHS, a_widths);
+		cell->setParam(ID::B_WIDTHS, b_widths);
+		cell->setParam(ID::C_WIDTHS, c_widths);
+		cell->setPort(ID::A, a);
+		cell->setPort(ID::B, b);
+		cell->setPort(ID::C, c);
 	}
 
 	bool eval(RTLIL::Const &result) const

kernel/register.cc

@@ -20,71 +20,13 @@
 #include "kernel/yosys.h"
 #include "kernel/satgen.h"
 #include "kernel/json.h"
+#include "kernel/gzip.h"
 
 #include <string.h>
 #include <stdlib.h>
 #include <stdio.h>
 #include <errno.h>
 
-#ifdef YOSYS_ENABLE_ZLIB
-#include <zlib.h>
-
-PRIVATE_NAMESPACE_BEGIN
-#define GZ_BUFFER_SIZE 8192
-void decompress_gzip(const std::string &filename, std::stringstream &out)
-{
-	char buffer[GZ_BUFFER_SIZE];
-	int bytes_read;
-	gzFile gzf = gzopen(filename.c_str(), "rb");
-	while(!gzeof(gzf)) {
-		bytes_read = gzread(gzf, reinterpret_cast<void *>(buffer), GZ_BUFFER_SIZE);
-		out.write(buffer, bytes_read);
-	}
-	gzclose(gzf);
-}
-
-/*
-An output stream that uses a stringbuf to buffer data internally,
-using zlib to write gzip-compressed data every time the stream is flushed.
-*/
-class gzip_ostream : public std::ostream  {
-public:
-	gzip_ostream() : std::ostream(nullptr)
-	{
-		rdbuf(&outbuf);
-	}
-	bool open(const std::string &filename)
-	{
-		return outbuf.open(filename);
-	}
-private:
-	class gzip_streambuf : public std::stringbuf {
-	public:
-		gzip_streambuf() { };
-		bool open(const std::string &filename)
-		{
-			gzf = gzopen(filename.c_str(), "wb");
-			return gzf != nullptr;
-		}
-		virtual int sync() override
-		{
-			gzwrite(gzf, reinterpret_cast<const void *>(str().c_str()), unsigned(str().size()));
-			str("");
-			return 0;
-		}
-		virtual ~gzip_streambuf()
-		{
-			sync();
-			gzclose(gzf);
-		}
-	private:
-		gzFile gzf = nullptr;
-	} outbuf;
-};
-PRIVATE_NAMESPACE_END
-
-#endif
-
 YOSYS_NAMESPACE_BEGIN
 
 #define MAX_REG_COUNT 1000
@@ -527,44 +469,8 @@ void Frontend::extra_args(std::istream *&f, std::string &filename, std::vector<s
 				next_args.insert(next_args.end(), args.begin(), args.begin()+argidx);
 				next_args.insert(next_args.end(), filenames.begin()+1, filenames.end());
 			}
-			std::ifstream *ff = new std::ifstream;
-			ff->open(filename.c_str(), bin_input ? std::ifstream::binary : std::ifstream::in);
 			yosys_input_files.insert(filename);
-			if (ff->fail()) {
-				delete ff;
-				ff = nullptr;
-			}
-			f = ff;
-			if (f != NULL) {
-				// Check for gzip magic
-				unsigned char magic[3];
-				int n = 0;
-				while (n < 3)
-				{
-					int c = ff->get();
-					if (c != EOF) {
-						magic[n] = (unsigned char) c;
-					}
-					n++;
-				}
-				if (n == 3 && magic[0] == 0x1f && magic[1] == 0x8b) {
-	#ifdef YOSYS_ENABLE_ZLIB
-					log("Found gzip magic in file `%s', decompressing using zlib.\n", filename.c_str());
-					if (magic[2] != 8)
-						log_cmd_error("gzip file `%s' uses unsupported compression type %02x\n",
-							filename.c_str(), unsigned(magic[2]));
-					delete ff;
-					std::stringstream *df = new std::stringstream();
-					decompress_gzip(filename, *df);
-					f = df;
-	#else
-					log_cmd_error("File `%s' is a gzip file, but Yosys is compiled without zlib.\n", filename.c_str());
-	#endif
-				} else {
-					ff->clear();
-					ff->seekg(0, std::ios::beg);
-				}
-			}
+			f = uncompressed(filename, bin_input ? std::ifstream::binary : std::ifstream::in);
 		}
 		if (f == NULL)
 			log_cmd_error("Can't open input file `%s' for reading: %s\n", filename.c_str(), strerror(errno));

kernel/rtlil.cc

@@ -540,6 +540,12 @@ void RTLIL::Const::bitvectorize() const {
 	}
 }
 
+void RTLIL::Const::append(const RTLIL::Const &other) {
+	bitvectorize();
+	bitvectype& bv = get_bits();
+	bv.insert(bv.end(), other.begin(), other.end());
+}
+
 RTLIL::State RTLIL::Const::const_iterator::operator*() const {
 	if (auto bv = parent.get_if_bits())
 		return (*bv)[idx];
@@ -1461,6 +1467,40 @@ namespace {
 				return;
 			}
 
+			if (cell->type == ID($macc_v2)) {
+				if (param(ID::NPRODUCTS) < 0)
+					error(__LINE__);
+				if (param(ID::NADDENDS) < 0)
+					error(__LINE__);
+				param_bits(ID::PRODUCT_NEGATED, max(param(ID::NPRODUCTS), 1));
+				param_bits(ID::ADDEND_NEGATED, max(param(ID::NADDENDS), 1));
+				param_bits(ID::A_SIGNED, max(param(ID::NPRODUCTS), 1));
+				param_bits(ID::B_SIGNED, max(param(ID::NPRODUCTS), 1));
+				param_bits(ID::C_SIGNED, max(param(ID::NADDENDS), 1));
+				if (cell->getParam(ID::A_SIGNED) != cell->getParam(ID::B_SIGNED))
+					error(__LINE__);
+				param_bits(ID::A_WIDTHS, max(param(ID::NPRODUCTS) * 16, 1));
+				param_bits(ID::B_WIDTHS, max(param(ID::NPRODUCTS) * 16, 1));
+				param_bits(ID::C_WIDTHS, max(param(ID::NADDENDS) * 16, 1));
+				const Const &a_width = cell->getParam(ID::A_WIDTHS);
+				const Const &b_width = cell->getParam(ID::B_WIDTHS);
+				const Const &c_width = cell->getParam(ID::C_WIDTHS);
+				int a_width_sum = 0, b_width_sum = 0, c_width_sum = 0;
+				for (int i = 0; i < param(ID::NPRODUCTS); i++) {
+					a_width_sum += a_width.extract(16 * i, 16).as_int(false);
+					b_width_sum += b_width.extract(16 * i, 16).as_int(false);
+				}
+				for (int i = 0; i < param(ID::NADDENDS); i++) {
+					c_width_sum += c_width.extract(16 * i, 16).as_int(false);
+				}
+				port(ID::A, a_width_sum);
+				port(ID::B, b_width_sum);
+				port(ID::C, c_width_sum);
+				port(ID::Y, param(ID::Y_WIDTH));
+				check_expected();
+				return;
+			}
+
 			if (cell->type == ID($logic_not)) {
 				param_bool(ID::A_SIGNED);
 				port(ID::A, param(ID::A_WIDTH));
@@ -4093,6 +4133,11 @@ void RTLIL::Cell::fixup_parameters(bool set_a_signed, bool set_b_signed)
 		return;
 	}
 
+	if (type == ID($macc_v2)) {
+		parameters[ID::Y_WIDTH] = GetSize(connections_[ID::Y]);
+		return;
+	}
+
 	bool signedness_ab = !type.in(ID($slice), ID($concat), ID($macc));
 
 	if (connections_.count(ID::A)) {

kernel/rtlil.h

@@ -738,6 +738,8 @@ public:
 	bool empty() const;
 	void bitvectorize() const;
 
+	void append(const RTLIL::Const &other);
+
 	class const_iterator {
 	private:
 		const Const& parent;

kernel/satgen.cc

@@ -740,7 +740,7 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep)
 		return true;
 	}
 
-	if (cell->type == ID($macc))
+	if (cell->type.in(ID($macc), ID($macc_v2)))
 	{
 		std::vector<int> a = importDefSigSpec(cell->getPort(ID::A), timestep);
 		std::vector<int> y = importDefSigSpec(cell->getPort(ID::Y), timestep);

kernel/utils.h

@@ -262,6 +262,20 @@ struct arrow_proxy {
 	T* operator->() { return &v; }
 };
 
+inline int ceil_log2(int x)
+{
+#if defined(__GNUC__)
+        return x > 1 ? (8*sizeof(int)) - __builtin_clz(x-1) : 0;
+#else
+	if (x <= 0)
+		return 0;
+	for (int i = 0; i < 32; i++)
+		if (((x-1) >> i) == 0)
+			return i;
+	log_abort();
+#endif
+}
+
 YOSYS_NAMESPACE_END
 
 #endif

kernel/yosys.cc

@@ -147,151 +147,6 @@ void yosys_banner()
 	log(" %s\n", yosys_version_str);
 }
 
-int ceil_log2(int x)
-{
-#if defined(__GNUC__)
-        return x > 1 ? (8*sizeof(int)) - __builtin_clz(x-1) : 0;
-#else
-	if (x <= 0)
-		return 0;
-	for (int i = 0; i < 32; i++)
-		if (((x-1) >> i) == 0)
-			return i;
-	log_abort();
-#endif
-}
-
-int readsome(std::istream &f, char *s, int n)
-{
-	int rc = int(f.readsome(s, n));
-
-	// f.readsome() sometimes returns 0 on a non-empty stream..
-	if (rc == 0) {
-		int c = f.get();
-		if (c != EOF) {
-			*s = c;
-			rc = 1;
-		}
-	}
-
-	return rc;
-}
-
-std::string next_token(std::string &text, const char *sep, bool long_strings)
-{
-	size_t pos_begin = text.find_first_not_of(sep);
-
-	if (pos_begin == std::string::npos)
-		pos_begin = text.size();
-
-	if (long_strings && pos_begin != text.size() && text[pos_begin] == '"') {
-		string sep_string = sep;
-		for (size_t i = pos_begin+1; i < text.size(); i++) {
-			if (text[i] == '"' && (i+1 == text.size() || sep_string.find(text[i+1]) != std::string::npos)) {
-				std::string token = text.substr(pos_begin, i-pos_begin+1);
-				text = text.substr(i+1);
-				return token;
-			}
-			if (i+1 < text.size() && text[i] == '"' && text[i+1] == ';' && (i+2 == text.size() || sep_string.find(text[i+2]) != std::string::npos)) {
-				std::string token = text.substr(pos_begin, i-pos_begin+1);
-				text = text.substr(i+2);
-				return token + ";";
-			}
-		}
-	}
-
-	size_t pos_end = text.find_first_of(sep, pos_begin);
-
-	if (pos_end == std::string::npos)
-		pos_end = text.size();
-
-	std::string token = text.substr(pos_begin, pos_end-pos_begin);
-	text = text.substr(pos_end);
-	return token;
-}
-
-std::vector<std::string> split_tokens(const std::string &text, const char *sep)
-{
-	std::vector<std::string> tokens;
-	std::string current_token;
-	for (char c : text) {
-		if (strchr(sep, c)) {
-			if (!current_token.empty()) {
-				tokens.push_back(current_token);
-				current_token.clear();
-			}
-		} else
-			current_token += c;
-	}
-	if (!current_token.empty()) {
-		tokens.push_back(current_token);
-		current_token.clear();
-	}
-	return tokens;
-}
-
-// this is very similar to fnmatch(). the exact rules used by this
-// function are:
-//
-//    ?        matches any character except
-//    *        matches any sequence of characters
-//    [...]    matches any of the characters in the list
-//    [!..]    matches any of the characters not in the list
-//
-// a backslash may be used to escape the next characters in the
-// pattern. each special character can also simply match itself.
-//
-bool patmatch(const char *pattern, const char *string)
-{
-	if (*pattern == 0)
-		return *string == 0;
-
-	if (*pattern == '\\') {
-		if (pattern[1] == string[0] && patmatch(pattern+2, string+1))
-			return true;
-	}
-
-	if (*pattern == '?') {
-		if (*string == 0)
-			return false;
-		return patmatch(pattern+1, string+1);
-	}
-
-	if (*pattern == '*') {
-		while (*string) {
-			if (patmatch(pattern+1, string++))
-				return true;
-		}
-		return pattern[1] == 0;
-	}
-
-	if (*pattern == '[') {
-		bool found_match = false;
-		bool inverted_list = pattern[1] == '!';
-		const char *p = pattern + (inverted_list ? 1 : 0);
-
-		while (*++p) {
-			if (*p == ']') {
-				if (found_match != inverted_list && patmatch(p+1, string+1))
-					return true;
-				break;
-			}
-
-			if (*p == '\\') {
-				if (*++p == *string)
-					found_match = true;
-			} else
-			if (*p == *string)
-				found_match = true;
-		}
-	}
-
-	if (*pattern == *string)
-		return patmatch(pattern+1, string+1);
-
-	return false;
-}
-
 #if !defined(YOSYS_DISABLE_SPAWN)
 int run_command(const std::string &command, std::function<void(const std::string&)> process_line)
 {
@@ -323,228 +178,6 @@ int run_command(const std::string &command, std::function<void(const std::string
 }
 #endif
 
-std::string get_base_tmpdir()
-{
-	static std::string tmpdir;
-
-	if (!tmpdir.empty()) {
-		return tmpdir;
-	}
-
-#if defined(_WIN32)
-#  ifdef __MINGW32__
-	char longpath[MAX_PATH + 1];
-	char shortpath[MAX_PATH + 1];
-#  else
-	WCHAR longpath[MAX_PATH + 1];
-	TCHAR shortpath[MAX_PATH + 1];
-#  endif
-	if (!GetTempPath(MAX_PATH+1, longpath))
-		log_error("GetTempPath() failed.\n");
-	if (!GetShortPathName(longpath, shortpath, MAX_PATH + 1))
-		log_error("GetShortPathName() failed.\n");
-	for (int i = 0; shortpath[i]; i++)
-		tmpdir += char(shortpath[i]);
-#else
-	char * var = std::getenv("TMPDIR");
-	if (var && strlen(var)!=0) {
-		tmpdir.assign(var);
-		// We return the directory name without the trailing '/'
-		while (!tmpdir.empty() && (tmpdir.back() == '/')) {
-			tmpdir.pop_back();
-		}
-	} else {
-		tmpdir.assign("/tmp");
-	}
-#endif
-	return tmpdir;
-}
-
-std::string make_temp_file(std::string template_str)
-{
-	size_t pos = template_str.rfind("XXXXXX");
-	log_assert(pos != std::string::npos);
-#if defined(__wasm)
-	static size_t index = 0;
-	template_str.replace(pos, 6, stringf("%06zu", index++));
-#elif defined(_WIN32)
-#ifndef YOSYS_WIN32_UNIX_DIR
-	std::replace(template_str.begin(), template_str.end(), '/', '\\');
-#endif
-	while (1) {
-		for (int i = 0; i < 6; i++) {
-			static std::string y = "0123456789abcdefghijklmnopqrstuvwxyzABCDEFGHIJKLMNOPQRSTUVWXYZ";
-			static uint32_t x = 314159265 ^ uint32_t(time(NULL));
-			x ^= x << 13, x ^= x >> 17, x ^= x << 5;
-			template_str[pos+i] = y[x % y.size()];
-		}
-		if (_access(template_str.c_str(), 0) != 0)
-			break;
-	}
-#else
-	int suffixlen = GetSize(template_str) - pos - 6;
-
-	char *p = strdup(template_str.c_str());
-	close(mkstemps(p, suffixlen));
-	template_str = p;
-	free(p);
-#endif
-
-	return template_str;
-}
-
-std::string make_temp_dir(std::string template_str)
-{
-#if defined(_WIN32)
-	template_str = make_temp_file(template_str);
-	mkdir(template_str.c_str());
-	return template_str;
-#elif defined(__wasm)
-	template_str = make_temp_file(template_str);
-	mkdir(template_str.c_str(), 0777);
-	return template_str;
-#else
-#  ifndef NDEBUG
-	size_t pos = template_str.rfind("XXXXXX");
-	log_assert(pos != std::string::npos);
-
-	int suffixlen = GetSize(template_str) - pos - 6;
-	log_assert(suffixlen == 0);
-#  endif
-
-	char *p = strdup(template_str.c_str());
-	log_assert(p);
-	char *res = mkdtemp(p);
-	if (!res)
-		log_error("mkdtemp failed for '%s': %s [Error %d]\n",
-			p, strerror(errno), errno);
-	template_str = p;
-	free(p);
-
-	return template_str;
-#endif
-}
-
-bool check_directory_exists(const std::string& dirname)
-{
-#if defined(_WIN32)
-	struct _stat info;
-	if (_stat(dirname.c_str(), &info) != 0)
-	{
-		return false;
-	}
-	return (info.st_mode & _S_IFDIR) != 0;
-#else
-	struct stat info;
-	if (stat(dirname.c_str(), &info) != 0)
-	{
-		return false;
-	}
-	return (info.st_mode & S_IFDIR) != 0;
-#endif
-}
-
-#ifdef _WIN32
-bool check_file_exists(std::string filename, bool)
-{
-	return _access(filename.c_str(), 0) == 0;
-}
-#else
-bool check_file_exists(std::string filename, bool is_exec)
-{
-	return access(filename.c_str(), is_exec ? X_OK : F_OK) == 0;
-}
-#endif
-
-bool is_absolute_path(std::string filename)
-{
-#ifdef _WIN32
-	return filename[0] == '/' || filename[0] == '\\' || (filename[0] != 0 && filename[1] == ':');
-#else
-	return filename[0] == '/';
-#endif
-}
-
-void remove_directory(std::string dirname)
-{
-#ifdef _WIN32
-	run_command(stringf("rmdir /s /q \"%s\"", dirname.c_str()));
-#else
-	struct stat stbuf;
-	struct dirent **namelist;
-	int n = scandir(dirname.c_str(), &namelist, nullptr, alphasort);
-	log_assert(n >= 0);
-	for (int i = 0; i < n; i++) {
-		if (strcmp(namelist[i]->d_name, ".") && strcmp(namelist[i]->d_name, "..")) {
-			std::string buffer = stringf("%s/%s", dirname.c_str(), namelist[i]->d_name);
-			if (!stat(buffer.c_str(), &stbuf) && S_ISREG(stbuf.st_mode)) {
-				remove(buffer.c_str());
-			} else
-				remove_directory(buffer);
-		}
-		free(namelist[i]);
-	}
-	free(namelist);
-	rmdir(dirname.c_str());
-#endif
-}
-
-bool create_directory(const std::string& dirname)
-{
-#if defined(_WIN32)
-	int ret = _mkdir(dirname.c_str());
-#else
-	mode_t mode = 0755;
-	int ret = mkdir(dirname.c_str(), mode);
-#endif
-	if (ret == 0)
-		return true;
-
-	switch (errno)
-	{
-	case ENOENT:
-		// parent didn't exist, try to create it
-		{
-			std::string::size_type pos = dirname.find_last_of('/');
-			if (pos == std::string::npos)
-#if defined(_WIN32)
-				pos = dirname.find_last_of('\\');
-			if (pos == std::string::npos)
-#endif
-				return false;
-			if (!create_directory( dirname.substr(0, pos) ))
-				return false;
-		}
-		// now, try to create again
-#if defined(_WIN32)
-		return 0 == _mkdir(dirname.c_str());
-#else
-		return 0 == mkdir(dirname.c_str(), mode);
-#endif
-
-	case EEXIST:
-		// done!
-		return check_directory_exists(dirname);
-
-	default:
-		return false;
-	}
-}
-
-std::string escape_filename_spaces(const std::string& filename)
-{
-	std::string out;
-	out.reserve(filename.size());
-	for (auto c : filename)
-	{
-		if (c == ' ')
-			out += "\\ ";
-		else
-			out.push_back(c);
-	}
-	return out;
-}
-
 bool already_setup = false;
 
 void yosys_setup()

kernel/yosys_common.h

@@ -128,6 +128,13 @@
 #  error "C++17 or later compatible compiler is required"
 #endif
 
+#if defined(__has_cpp_attribute) && __has_cpp_attribute(gnu::cold)
+#  define YS_COLD [[gnu::cold]]
+#else
+#  define YS_COLD
+#endif
+
+#include "kernel/io.h"
 
 YOSYS_NAMESPACE_BEGIN
 
@@ -245,63 +252,6 @@ inline void memhasher() { if (memhasher_active) memhasher_do(); }
 void yosys_banner();
 int ceil_log2(int x) YS_ATTRIBUTE(const);
 
-inline std::string vstringf(const char *fmt, va_list ap)
-{
-        // For the common case of strings shorter than 128, save a heap
-        // allocation by using a stack allocated buffer.
-        const int kBufSize = 128;
-        char buf[kBufSize];
-        buf[0] = '\0';
-        va_list apc;
-        va_copy(apc, ap);
-        int n = vsnprintf(buf, kBufSize, fmt, apc);
-        va_end(apc);
-        if (n < kBufSize)
-          return std::string(buf);
-
-        std::string string;
-        char *str = NULL;
-#if defined(_WIN32 )|| defined(__CYGWIN__)
-        int sz = 2 * kBufSize, rc;
-        while (1) {
-		va_copy(apc, ap);
-		str = (char*)realloc(str, sz);
-		rc = vsnprintf(str, sz, fmt, apc);
-		va_end(apc);
-		if (rc >= 0 && rc < sz)
-			break;
-		sz *= 2;
-	}
-	if (str != NULL) {
-		string = str;
-		free(str);
-	}
-	return string;
-#else
-        if (vasprintf(&str, fmt, ap) < 0)
-          str = NULL;
-        if (str != NULL) {
-          string = str;
-          free(str);
-        }
-	return string;
-#endif
-}
-
-std::string stringf(const char *fmt, ...) YS_ATTRIBUTE(format(printf, 1, 2));
-
-inline std::string stringf(const char *fmt, ...)
-{
-	std::string string;
-	va_list ap;
-
-	va_start(ap, fmt);
-	string = vstringf(fmt, ap);
-	va_end(ap);
-
-	return string;
-}
-
 int readsome(std::istream &f, char *s, int n);
 std::string next_token(std::string &text, const char *sep = " \t\r\n", bool long_strings = false);
 std::vector<std::string> split_tokens(const std::string &text, const char *sep = " \t\r\n");

libs/ezsat/ezsat.cc

@@ -676,10 +676,10 @@ void ezSAT::preSolverCallback()
 bool ezSAT::solver(const std::vector<int>&, std::vector<bool>&, const std::vector<int>&)
 {
 	preSolverCallback();
-	fprintf(stderr, "************************************************************************\n");
-	fprintf(stderr, "ERROR: You are trying to use the solve() method of the ezSAT base class!\n");
+	fprintf(stderr, "*************************************************************************\n");
+	fprintf(stderr, "ERROR: You are trying to use the solver() method of the ezSAT base class!\n");
 	fprintf(stderr, "Use a dervied class like ezMiniSAT instead.\n");
-	fprintf(stderr, "************************************************************************\n");
+	fprintf(stderr, "*************************************************************************\n");
 	abort();
 }
 
@@ -1332,7 +1332,7 @@ void ezSAT::printInternalState(FILE *f) const
 		fprintf(f, "\n");
 	}
 	if (cnfConsumed)
-		fprintf(f, " *** more clauses consumed via cnfConsume() ***\n");
+		fprintf(f, " *** more clauses consumed via consumeCnf() ***\n");
 
 	fprintf(f, "--8<-- snap --8<--\n");
 }

libs/fst/00_PATCH_i386_endian.patch

@@ -0,0 +1,14 @@
+--- fstapi.cc
++++ fstapi.cc
+@@ -4723,7 +4723,10 @@ if(gzread_pass_status)
+                                 hdr_incomplete = (xc->start_time == 0) && (xc->end_time == 0);
+ 
+                                 fstFread(&dcheck, 8, 1, xc->f);
+-                                xc->double_endian_match = (dcheck == FST_DOUBLE_ENDTEST);
++				/*
++				 * Yosys patch: Fix double endian check for i386 targets built in modern gcc
++				 */
++                                xc->double_endian_match = (dcheck == (double)FST_DOUBLE_ENDTEST);
+                                 if(!xc->double_endian_match)
+                                         {
+                                         union   {

libs/fst/00_UPDATE.sh

@@ -19,3 +19,4 @@ patch -p0 < 00_PATCH_win_zlib.patch
 patch -p0 < 00_PATCH_win_io.patch
 patch -p1 < 00_PATCH_strict_alignment.patch
 patch -p0 < 00_PATCH_wx_len_overread.patch
+patch -p0 < 00_PATCH_i386_endian.patch

libs/fst/fstapi.cc

@@ -4723,7 +4723,10 @@ if(gzread_pass_status)
                                 hdr_incomplete = (xc->start_time == 0) && (xc->end_time == 0);
 
                                 fstFread(&dcheck, 8, 1, xc->f);
-                                xc->double_endian_match = (dcheck == FST_DOUBLE_ENDTEST);
+				/*
+				 * Yosys patch: Fix double endian check for i386 targets built in modern gcc
+				 */
+                                xc->double_endian_match = (dcheck == (double)FST_DOUBLE_ENDTEST);
                                 if(!xc->double_endian_match)
                                         {
                                         union   {

misc/yosys-config.in

@@ -36,12 +36,12 @@ help() {
 		echo ""
 		echo "  $0 --datdir/simlib.v"
 		echo ""
-	} >&2
-	exit 1
+	} >&$(( $1 + 1))
+	exit $1
 }
 
 if [ $# -eq 0 ]; then
-	help
+	help 1
 fi
 
 if [ "$1" = "--build" ]; then
@@ -83,7 +83,7 @@ for opt; do
 			tokens=( "${tokens[@]}" '@DATDIR@'"${opt#${prefix}datdir}" ) ;;
 		--help|-\?|-h)
 			if [ ${#tokens[@]} -eq 0 ]; then
-				help
+				help 0
 			else
 				tokens=( "${tokens[@]}" "$opt" )
 			fi ;;

passes/cmds/abstract.cc

@@ -45,9 +45,9 @@ struct Slice {
 	}
 
 	static int parse_index(const char *begin, const char *end, const std::string &slice) {
-		int value;
+		int value = 0;
 		auto result = std::from_chars(begin, end, value, 10);
-        if (result.ptr != end || result.ptr == begin)
+		if (result.ptr != end || result.ptr == begin)
 			syntax_error(slice);
 		return value;
 	}

passes/cmds/dft_tag.cc

@@ -883,7 +883,7 @@ struct DftTagWorker {
 	{
 		if (sig_a.is_fully_const()) {
 			auto const_val = sig_a.as_const();
-			for (auto bit : const_val)
+			for (State& bit : const_val.bits())
 				bit = bit == State::S0 ? State::S1 : bit == State::S1 ? State::S0 : bit;
 			return const_val;
 		}

passes/cmds/setundef.cc

@@ -243,7 +243,7 @@ struct SetundefPass : public Pass {
 			{
 				for (auto *cell : module->selected_cells()) {
 					for (auto &parameter : cell->parameters) {
-						for (auto bit : parameter.second) {
+						for (auto &bit : parameter.second.bits()) {
 							if (bit > RTLIL::State::S1)
 								bit = worker.next_bit();
 						}

passes/cmds/splitcells.cc

@@ -103,8 +103,7 @@ struct SplitcellsWorker
 
 				auto slice_signal = [&](SigSpec old_sig) -> SigSpec {
 					SigSpec new_sig;
-					for (int i = 0; i < GetSize(old_sig); i += GetSize(outsig)) {
-						int offset = i+slice_lsb;
+					for (int offset = slice_lsb; offset < GetSize(old_sig); offset += GetSize(outsig)) {
 						int length = std::min(GetSize(old_sig)-offset, slice_msb-slice_lsb+1);
 						new_sig.append(old_sig.extract(offset, length));
 					}

passes/cmds/stat.cc

@@ -23,6 +23,7 @@
 #include "kernel/celltypes.h"
 #include "passes/techmap/libparse.h"
 #include "kernel/cost.h"
+#include "kernel/gzip.h"
 #include "libs/json11/json11.hpp"
 
 USING_YOSYS_NAMESPACE
@@ -347,13 +348,12 @@ statdata_t hierarchy_worker(std::map<RTLIL::IdString, statdata_t> &mod_stat, RTL
 
 void read_liberty_cellarea(dict<IdString, cell_area_t> &cell_area, string liberty_file)
 {
-	std::ifstream f;
-	f.open(liberty_file.c_str());
+	std::istream* f = uncompressed(liberty_file.c_str());
 	yosys_input_files.insert(liberty_file);
-	if (f.fail())
+	if (f->fail())
 		log_cmd_error("Can't open liberty file `%s': %s\n", liberty_file.c_str(), strerror(errno));
-	LibertyParser libparser(f);
-	f.close();
+	LibertyParser libparser(*f, liberty_file);
+	delete f;
 
 	for (auto cell : libparser.ast->children)
 	{

passes/fsm/fsm_recode.cc

@@ -22,6 +22,7 @@
 #include "kernel/sigtools.h"
 #include "kernel/consteval.h"
 #include "kernel/celltypes.h"
+#include "kernel/utils.h"
 #include "fsmdata.h"
 #include <math.h>
 #include <string.h>

passes/opt/opt_expr.cc

@@ -1573,6 +1573,20 @@ skip_identity:
 			}
 		}
 
+		if (mux_undef && cell->type.in(ID($_MUX4_), ID($_MUX8_), ID($_MUX16_))) {
+			int num_inputs = 4;
+			if (cell->type == ID($_MUX8_)) num_inputs = 8;
+			if (cell->type == ID($_MUX16_)) num_inputs = 16;
+			int undef_inputs = 0;
+			for (auto &conn : cell->connections())
+				if (!conn.first.in(ID::S, ID::T, ID::U, ID::V, ID::Y))
+					undef_inputs += conn.second.is_fully_undef();
+			if (undef_inputs == num_inputs) {
+				replace_cell(assign_map, module, cell, "mux_undef", ID::Y, cell->getPort(ID::A));
+				goto next_cell;
+			}
+		}
+
 #define FOLD_1ARG_CELL(_t) \
 		if (cell->type == ID($##_t)) { \
 			RTLIL::SigSpec a = cell->getPort(ID::A); \
@@ -1690,7 +1704,38 @@ skip_identity:
 			else if (inA == inB)
 				ACTION_DO(ID::Y, cell->getPort(ID::A));
 		}
+		if (cell->type == ID($pow) && cell->getPort(ID::A).is_fully_const() && !cell->parameters[ID::B_SIGNED].as_bool()) {
+			SigSpec sig_a = assign_map(cell->getPort(ID::A));
+			SigSpec sig_y = assign_map(cell->getPort(ID::Y));
+			int y_size = GetSize(sig_y);
 
+			int bit_idx;
+			const auto onehot = sig_a.is_onehot(&bit_idx);
+
+			if (onehot) {
+				if (bit_idx == 1) {
+					log_debug("Replacing pow cell `%s' in module `%s' with left-shift\n", 
+							cell->name.c_str(), module->name.c_str());
+					cell->type = ID($shl);
+					cell->parameters[ID::A_WIDTH] = 1;
+					cell->setPort(ID::A, Const(State::S1, 1));
+				}
+				else {
+					log_debug("Replacing pow cell `%s' in module `%s' with multiply and left-shift\n", 
+							cell->name.c_str(), module->name.c_str());
+					cell->type = ID($mul);
+					cell->parameters[ID::A_SIGNED] = 0;
+					cell->setPort(ID::A, Const(bit_idx, cell->parameters[ID::A_WIDTH].as_int()));
+					
+					SigSpec y_wire = module->addWire(NEW_ID, y_size);
+					cell->setPort(ID::Y, y_wire);
+					
+					module->addShl(NEW_ID, Const(State::S1, 1), y_wire, sig_y);
+				}
+				did_something = true;
+				goto next_cell;
+			}
+		}
 		if (!keepdc && cell->type == ID($mul))
 		{
 			bool a_signed = cell->parameters[ID::A_SIGNED].as_bool();

passes/opt/opt_merge.cc

@@ -26,6 +26,8 @@
 #include <stdlib.h>
 #include <stdio.h>
 #include <set>
+#include <unordered_map>
+#include <array>
 
 
 USING_YOSYS_NAMESPACE
@@ -42,6 +44,22 @@ struct OptMergeWorker
 	CellTypes ct;
 	int total_count;
 
+	static vector<pair<SigBit, SigSpec>> sorted_pmux_in(const dict<RTLIL::IdString, RTLIL::SigSpec> &conn)
+	{
+		SigSpec sig_s = conn.at(ID::S);
+		SigSpec sig_b = conn.at(ID::B);
+
+		int s_width = GetSize(sig_s);
+		int width = GetSize(sig_b) / s_width;
+
+		vector<pair<SigBit, SigSpec>> sb_pairs;
+		for (int i = 0; i < s_width; i++)
+			sb_pairs.push_back(pair<SigBit, SigSpec>(sig_s[i], sig_b.extract(i*width, width)));
+
+		std::sort(sb_pairs.begin(), sb_pairs.end());
+		return sb_pairs;
+	}
+
 	static void sort_pmux_conn(dict<RTLIL::IdString, RTLIL::SigSpec> &conn)
 	{
 		SigSpec sig_s = conn.at(ID::S);
@@ -65,95 +83,78 @@ struct OptMergeWorker
 		}
 	}
 
-	std::string int_to_hash_string(unsigned int v)
+	Hasher hash_cell_inputs(const RTLIL::Cell *cell, Hasher h) const
 	{
-		if (v == 0)
-			return "0";
-		std::string str = "";
-		while (v > 0) {
-			str += 'a' + (v & 15);
-			v = v >> 4;
-		}
-		return str;
-	}
-
-        uint64_t hash_cell_parameters_and_connections(const RTLIL::Cell *cell)
-	{
-		vector<string> hash_conn_strings;
-		std::string hash_string = cell->type.str() + "\n";
-
-		const dict<RTLIL::IdString, RTLIL::SigSpec> *conn = &cell->connections();
-		dict<RTLIL::IdString, RTLIL::SigSpec> alt_conn;
-
+		// TODO: when implemented, use celltypes to match:
+		// (builtin || stdcell) && (unary || binary) && symmetrical
 		if (cell->type.in(ID($and), ID($or), ID($xor), ID($xnor), ID($add), ID($mul),
 				ID($logic_and), ID($logic_or), ID($_AND_), ID($_OR_), ID($_XOR_))) {
-			alt_conn = *conn;
-			if (assign_map(alt_conn.at(ID::A)) < assign_map(alt_conn.at(ID::B))) {
-				alt_conn[ID::A] = conn->at(ID::B);
-				alt_conn[ID::B] = conn->at(ID::A);
+			std::array<RTLIL::SigSpec, 2> inputs = {
+				assign_map(cell->getPort(ID::A)),
+				assign_map(cell->getPort(ID::B))
+			};
+			std::sort(inputs.begin(), inputs.end());
+			h = hash_ops<std::array<RTLIL::SigSpec, 2>>::hash_into(inputs, h);
+		} else if (cell->type.in(ID($reduce_xor), ID($reduce_xnor))) {
+			SigSpec a = assign_map(cell->getPort(ID::A));
+			a.sort();
+			h = a.hash_into(h);
+		} else if (cell->type.in(ID($reduce_and), ID($reduce_or), ID($reduce_bool))) {
+			SigSpec a = assign_map(cell->getPort(ID::A));
+			a.sort_and_unify();
+			h = a.hash_into(h);
+		} else if (cell->type == ID($pmux)) {
+			dict<RTLIL::IdString, RTLIL::SigSpec> conn = cell->connections();
+			assign_map.apply(conn.at(ID::A));
+			assign_map.apply(conn.at(ID::B));
+			assign_map.apply(conn.at(ID::S));
+			for (const auto& [s_bit, b_chunk] : sorted_pmux_in(conn)) {
+				h = s_bit.hash_into(h);
+				h = b_chunk.hash_into(h);
 			}
-			conn = &alt_conn;
-		} else
-		if (cell->type.in(ID($reduce_xor), ID($reduce_xnor))) {
-			alt_conn = *conn;
-			assign_map.apply(alt_conn.at(ID::A));
-			alt_conn.at(ID::A).sort();
-			conn = &alt_conn;
-		} else
-		if (cell->type.in(ID($reduce_and), ID($reduce_or), ID($reduce_bool))) {
-			alt_conn = *conn;
-			assign_map.apply(alt_conn.at(ID::A));
-			alt_conn.at(ID::A).sort_and_unify();
-			conn = &alt_conn;
-		} else
-		if (cell->type == ID($pmux)) {
-			alt_conn = *conn;
-			assign_map.apply(alt_conn.at(ID::A));
-			assign_map.apply(alt_conn.at(ID::B));
-			assign_map.apply(alt_conn.at(ID::S));
-			sort_pmux_conn(alt_conn);
-			conn = &alt_conn;
-		}
-
-		for (auto &it : *conn) {
-			RTLIL::SigSpec sig;
-			if (cell->output(it.first)) {
-				if (it.first == ID::Q && RTLIL::builtin_ff_cell_types().count(cell->type)) {
-					// For the 'Q' output of state elements,
-					//   use its (* init *) attribute value
-					sig = initvals(it.second);
+			h = assign_map(cell->getPort(ID::A)).hash_into(h);
+		} else {
+			std::vector<std::pair<IdString, SigSpec>> conns;
+			for (const auto& conn : cell->connections()) {
+				conns.push_back(conn);
+			}
+			std::sort(conns.begin(), conns.end());
+			for (const auto& [port, sig] : conns) {
+				if (!cell->output(port)) {
+					h = port.hash_into(h);
+					h = assign_map(sig).hash_into(h);
 				}
-				else
-					continue;
 			}
-			else
-				sig = assign_map(it.second);
-			string s = "C " + it.first.str() + "=";
-			for (auto &chunk : sig.chunks()) {
-				if (chunk.wire)
-					s += "{" + chunk.wire->name.str() + " " +
-							int_to_hash_string(chunk.offset) + " " +
-							int_to_hash_string(chunk.width) + "}";
-				else
-					s += RTLIL::Const(chunk.data).as_string();
-			}
-			hash_conn_strings.push_back(s + "\n");
+
+			if (RTLIL::builtin_ff_cell_types().count(cell->type))
+				h = initvals(cell->getPort(ID::Q)).hash_into(h);
+
 		}
-
-		for (auto &it : cell->parameters)
-			hash_conn_strings.push_back("P " + it.first.str() + "=" + it.second.as_string() + "\n");
-
-		std::sort(hash_conn_strings.begin(), hash_conn_strings.end());
-
-		for (auto it : hash_conn_strings)
-			hash_string += it;
-
-		return std::hash<std::string>{}(hash_string);
+		return h;
 	}
 
-	bool compare_cell_parameters_and_connections(const RTLIL::Cell *cell1, const RTLIL::Cell *cell2)
+	static Hasher hash_cell_parameters(const RTLIL::Cell *cell, Hasher h)
 	{
-		log_assert(cell1 != cell2);
+		using Paramvec = std::vector<std::pair<IdString, Const>>;
+		Paramvec params;
+		for (const auto& param : cell->parameters) {
+			params.push_back(param);
+		}
+		std::sort(params.begin(), params.end());
+		return hash_ops<Paramvec>::hash_into(params, h);
+	}
+
+	Hasher hash_cell_function(const RTLIL::Cell *cell, Hasher h) const
+	{
+		h.eat(cell->type);
+		h = hash_cell_inputs(cell, h);
+		h = hash_cell_parameters(cell, h);
+		return h;
+	}
+
+	bool compare_cell_parameters_and_connections(const RTLIL::Cell *cell1, const RTLIL::Cell *cell2) const
+	{
+		if (cell1 == cell2) return true;
 		if (cell1->type != cell2->type) return false;
 
 		if (cell1->parameters != cell2->parameters)
@@ -252,21 +253,51 @@ struct OptMergeWorker
 		initvals.set(&assign_map, module);
 
 		bool did_something = true;
+		// A cell may have to go through a lot of collisions if the hash
+		// function is performing poorly, but it's a symptom of something bad
+		// beyond the user's control.
 		while (did_something)
 		{
 			std::vector<RTLIL::Cell*> cells;
-			cells.reserve(module->cells_.size());
-			for (auto &it : module->cells_) {
-				if (!design->selected(module, it.second))
+			cells.reserve(module->cells().size());
+			for (auto cell : module->cells()) {
+				if (!design->selected(module, cell))
 					continue;
-				if (mode_keepdc && has_dont_care_initval(it.second))
+				if (cell->type.in(ID($meminit), ID($meminit_v2), ID($mem), ID($mem_v2))) {
+					// Ignore those for performance: meminit can have an excessively large port,
+					// mem can have an excessively large parameter holding the init data
 					continue;
-				if (ct.cell_known(it.second->type) || (mode_share_all && it.second->known()))
-					cells.push_back(it.second);
+				}
+				if (mode_keepdc && has_dont_care_initval(cell))
+					continue;
+				if (ct.cell_known(cell->type) || (mode_share_all && cell->known()))
+					cells.push_back(cell);
 			}
 
 			did_something = false;
-                        dict<uint64_t, RTLIL::Cell*> sharemap;
+
+			// We keep a set of known cells. They're hashed with our hash_cell_function
+			// and compared with our compare_cell_parameters_and_connections.
+			// Both need to capture OptMergeWorker to access initvals
+			struct CellPtrHash {
+				const OptMergeWorker& worker;
+				CellPtrHash(const OptMergeWorker& w) : worker(w) {}
+				std::size_t operator()(const Cell* c) const {
+					return (std::size_t)worker.hash_cell_function(c, Hasher()).yield();
+				}
+			};
+			struct CellPtrEqual {
+				const OptMergeWorker& worker;
+				CellPtrEqual(const OptMergeWorker& w) : worker(w) {}
+				bool operator()(const Cell* lhs, const Cell* rhs) const {
+					return worker.compare_cell_parameters_and_connections(lhs, rhs);
+				}
+			};
+			std::unordered_set<
+				RTLIL::Cell*,
+				CellPtrHash,
+				CellPtrEqual> known_cells (0, CellPtrHash(*this), CellPtrEqual(*this));
+
 			for (auto cell : cells)
 			{
 				if ((!mode_share_all && !ct.cell_known(cell->type)) || !cell->known())
@@ -275,36 +306,36 @@ struct OptMergeWorker
 				if (cell->type == ID($scopeinfo))
 					continue;
 
-				uint64_t hash = hash_cell_parameters_and_connections(cell);
-				auto r = sharemap.insert(std::make_pair(hash, cell));
-				if (!r.second) {
-					if (compare_cell_parameters_and_connections(cell, r.first->second)) {
-						if (cell->has_keep_attr()) {
-							if (r.first->second->has_keep_attr())
-								continue;
-							std::swap(r.first->second, cell);
-						}
-
-
-						did_something = true;
-						log_debug("  Cell `%s' is identical to cell `%s'.\n", cell->name.c_str(), r.first->second->name.c_str());
-						for (auto &it : cell->connections()) {
-							if (cell->output(it.first)) {
-								RTLIL::SigSpec other_sig = r.first->second->getPort(it.first);
-								log_debug("    Redirecting output %s: %s = %s\n", it.first.c_str(),
-										log_signal(it.second), log_signal(other_sig));
-								Const init = initvals(other_sig);
-								initvals.remove_init(it.second);
-								initvals.remove_init(other_sig);
-								module->connect(RTLIL::SigSig(it.second, other_sig));
-								assign_map.add(it.second, other_sig);
-								initvals.set_init(other_sig, init);
-							}
-						}
-						log_debug("    Removing %s cell `%s' from module `%s'.\n", cell->type.c_str(), cell->name.c_str(), module->name.c_str());
-						module->remove(cell);
-						total_count++;
+				auto [cell_in_map, inserted] = known_cells.insert(cell);
+				if (!inserted) {
+					// We've failed to insert since we already have an equivalent cell
+					Cell* other_cell = *cell_in_map;
+					if (cell->has_keep_attr()) {
+						if (other_cell->has_keep_attr())
+							continue;
+						known_cells.erase(other_cell);
+						known_cells.insert(cell);
+						std::swap(other_cell, cell);
 					}
+
+					did_something = true;
+					log_debug("  Cell `%s' is identical to cell `%s'.\n", cell->name.c_str(), other_cell->name.c_str());
+					for (auto &it : cell->connections()) {
+						if (cell->output(it.first)) {
+							RTLIL::SigSpec other_sig = other_cell->getPort(it.first);
+							log_debug("    Redirecting output %s: %s = %s\n", it.first.c_str(),
+									log_signal(it.second), log_signal(other_sig));
+							Const init = initvals(other_sig);
+							initvals.remove_init(it.second);
+							initvals.remove_init(other_sig);
+							module->connect(RTLIL::SigSig(it.second, other_sig));
+							assign_map.add(it.second, other_sig);
+							initvals.set_init(other_sig, init);
+						}
+					}
+					log_debug("    Removing %s cell `%s' from module `%s'.\n", cell->type.c_str(), cell->name.c_str(), module->name.c_str());
+					module->remove(cell);
+					total_count++;
 				}
 			}
 		}

passes/opt/peepopt.cc

@@ -19,6 +19,7 @@
 
 #include "kernel/yosys.h"
 #include "kernel/sigtools.h"
+#include "kernel/utils.h"
 
 USING_YOSYS_NAMESPACE
 PRIVATE_NAMESPACE_BEGIN

passes/opt/pmux2shiftx.cc

@@ -20,6 +20,7 @@
 #include "kernel/yosys.h"
 #include "kernel/sigtools.h"
 #include "kernel/ffinit.h"
+#include "kernel/utils.h"
 
 USING_YOSYS_NAMESPACE
 PRIVATE_NAMESPACE_BEGIN

passes/opt/share.cc

@@ -23,6 +23,7 @@
 #include "kernel/modtools.h"
 #include "kernel/utils.h"
 #include "kernel/macc.h"
+#include <iterator>
 
 USING_YOSYS_NAMESPACE
 PRIVATE_NAMESPACE_BEGIN
@@ -33,6 +34,7 @@ typedef std::pair<RTLIL::SigSpec, RTLIL::Const> ssc_pair_t;
 struct ShareWorkerConfig
 {
 	int limit;
+	size_t pattern_limit;
 	bool opt_force;
 	bool opt_aggressive;
 	bool opt_fast;
@@ -853,6 +855,23 @@ struct ShareWorker
 		optimize_activation_patterns(patterns);
 	}
 
+	template<typename Iterator>
+	bool insert_capped(pool<ssc_pair_t>& cache, Iterator begin_pattern, Iterator end_pattern)
+	{
+		if (cache.size() + std::distance(begin_pattern, end_pattern) > config.pattern_limit) {
+			cache.clear();
+			cache.insert(ssc_pair_t());
+			return false;
+		} else {
+			cache.insert(begin_pattern, end_pattern);
+		}
+		return true;
+	}
+	bool insert_capped(pool<ssc_pair_t>& cache, ssc_pair_t pattern)
+	{
+		return insert_capped(cache, &pattern, &pattern + 1);
+	}
+
 	const pool<ssc_pair_t> &find_cell_activation_patterns(RTLIL::Cell *cell, const char *indent)
 	{
 		if (recursion_state.count(cell)) {
@@ -909,20 +928,29 @@ struct ShareWorker
 					for (int i = 0; i < GetSize(sig_s); i++)
 						p.first.append(sig_s[i]), p.second.bits().push_back(RTLIL::State::S0);
 					if (sort_check_activation_pattern(p))
-						activation_patterns_cache[cell].insert(p);
+						if (!insert_capped(activation_patterns_cache[cell], p)) {
+							recursion_state.erase(cell);
+							return activation_patterns_cache[cell];
+						}
 				}
 
 			for (int idx : used_in_b_parts)
 				for (auto p : c_patterns) {
 					p.first.append(sig_s[idx]), p.second.bits().push_back(RTLIL::State::S1);
 					if (sort_check_activation_pattern(p))
-						activation_patterns_cache[cell].insert(p);
+					if (!insert_capped(activation_patterns_cache[cell], p)) {
+						recursion_state.erase(cell);
+						return activation_patterns_cache[cell];
+					}
 				}
 		}
 
 		for (auto c : driven_cells) {
 			const pool<ssc_pair_t> &c_patterns = find_cell_activation_patterns(c, indent);
-			activation_patterns_cache[cell].insert(c_patterns.begin(), c_patterns.end());
+			if (!insert_capped(activation_patterns_cache[cell], c_patterns.begin(), c_patterns.end())) {
+				recursion_state.erase(cell);
+				return activation_patterns_cache[cell];
+			}
 		}
 
 		log_assert(recursion_state.count(cell) != 0);
@@ -1297,8 +1325,8 @@ struct ShareWorker
 
 				qcsat.ez->assume(qcsat.ez->AND(sub1, sub2));
 
-				log("      Size of SAT problem: %d variables, %d clauses\n",
-						qcsat.ez->numCnfVariables(), qcsat.ez->numCnfClauses());
+				log("      Size of SAT problem: %zu cells, %d variables, %d clauses\n",
+						qcsat.imported_cells.size(), qcsat.ez->numCnfVariables(), qcsat.ez->numCnfClauses());
 
 				if (qcsat.ez->solve(sat_model, sat_model_values)) {
 					log("      According to the SAT solver this pair of cells can not be shared.\n");
@@ -1438,12 +1466,18 @@ struct SharePass : public Pass {
 		log("  -limit N\n");
 		log("    Only perform the first N merges, then stop. This is useful for debugging.\n");
 		log("\n");
+		log("  -pattern-limit N\n");
+		log("    Only analyze up to N activation patterns per cell, otherwise assume active.\n");
+		log("    N is 1000 by default. Higher values may merge more resources at the cost of\n");
+		log("    more runtime and memory consumption.\n");
+		log("\n");
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{
 		ShareWorkerConfig config;
 
 		config.limit = -1;
+		config.pattern_limit = design->scratchpad_get_int("share.pattern_limit", 1000);
 		config.opt_force = false;
 		config.opt_aggressive = false;
 		config.opt_fast = false;
@@ -1508,6 +1542,10 @@ struct SharePass : public Pass {
 				config.limit = atoi(args[++argidx].c_str());
 				continue;
 			}
+			if (args[argidx] == "-pattern-limit" && argidx+1 < args.size()) {
+				config.pattern_limit = atoi(args[++argidx].c_str());
+				continue;
+			}
 			break;
 		}
 		extra_args(args, argidx, design);

passes/opt/wreduce.cc

@@ -21,6 +21,7 @@
 #include "kernel/sigtools.h"
 #include "kernel/modtools.h"
 #include "kernel/ffinit.h"
+#include "kernel/utils.h"
 
 USING_YOSYS_NAMESPACE
 

passes/pmgen/pmgen.py

@@ -354,6 +354,7 @@ with open(outfile, "w") as f:
     if genhdr:
         print("#include \"kernel/yosys.h\"", file=f)
         print("#include \"kernel/sigtools.h\"", file=f)
+        print("#include \"kernel/utils.h\"", file=f)
         print("", file=f)
         print("YOSYS_NAMESPACE_BEGIN", file=f)
         print("", file=f)

passes/sat/assertpmux.cc

@@ -19,6 +19,7 @@
 
 #include "kernel/yosys.h"
 #include "kernel/sigtools.h"
+#include "kernel/utils.h"
 
 USING_YOSYS_NAMESPACE
 PRIVATE_NAMESPACE_BEGIN

passes/sat/cutpoint.cc

@@ -34,8 +34,8 @@ struct CutpointPass : public Pass {
 		log("This command adds formal cut points to the design.\n");
 		log("\n");
 		log("    -undef\n");
-		log("        set cupoint nets to undef (x). the default behavior is to create a\n");
-		log("        $anyseq cell and drive the cutpoint net from that\n");
+		log("        set cutpoint nets to undef (x). the default behavior is to create\n");
+		log("        an $anyseq cell and drive the cutpoint net from that\n");
 		log("\n");
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override

passes/techmap/Makefile.inc

@@ -6,6 +6,7 @@ OBJS += passes/techmap/dfflibmap.o
 OBJS += passes/techmap/maccmap.o
 OBJS += passes/techmap/booth.o
 OBJS += passes/techmap/libparse.o
+OBJS += passes/techmap/libcache.o
 
 ifeq ($(ENABLE_ABC),1)
 OBJS += passes/techmap/abc.o

passes/techmap/booth.cc

@@ -218,7 +218,7 @@ struct BoothPassWorker {
 
 				log_assert(cell->getParam(ID::A_SIGNED).as_bool() == cell->getParam(ID::B_SIGNED).as_bool());
 				is_signed = cell->getParam(ID::A_SIGNED).as_bool();
-			} else if (cell->type == ID($macc)) {
+			} else if (cell->type.in(ID($macc), ID($macc_v2))) {
 				Macc macc;
 				macc.from_cell(cell);
 

passes/techmap/clockgate.cc

@@ -1,5 +1,6 @@
 #include "kernel/yosys.h"
 #include "kernel/ff.h"
+#include "kernel/gzip.h"
 #include "libparse.h"
 #include <optional>
 
@@ -308,13 +309,12 @@ struct ClockgatePass : public Pass {
 		if (!liberty_files.empty()) {
 			LibertyMergedCells merged;
 			for (auto path : liberty_files) {
-				std::ifstream f;
-				f.open(path.c_str());
-				if (f.fail())
+				std::istream* f = uncompressed(path);
+				if (f->fail())
 					log_cmd_error("Can't open liberty file `%s': %s\n", path.c_str(), strerror(errno));
-				LibertyParser p(f);
+				LibertyParser p(*f, path);
 				merged.merge(p);
-				f.close();
+				delete f;
 			}
 			std::tie(pos_icg_desc, neg_icg_desc) =
 				find_icgs(merged.cells, dont_use_cells);

passes/techmap/dfflibmap.cc

@@ -19,6 +19,7 @@
 
 #include "kernel/yosys.h"
 #include "kernel/sigtools.h"
+#include "kernel/gzip.h"
 #include "libparse.h"
 #include <string.h>
 #include <errno.h>
@@ -630,13 +631,12 @@ struct DfflibmapPass : public Pass {
 
 		LibertyMergedCells merged;
 		for (auto path : liberty_files) {
-			std::ifstream f;
-			f.open(path.c_str());
-			if (f.fail())
+			std::istream* f = uncompressed(path);
+			if (f->fail())
 				log_cmd_error("Can't open liberty file `%s': %s\n", path.c_str(), strerror(errno));
-			LibertyParser p(f);
+			LibertyParser p(*f, path);
 			merged.merge(p);
-			f.close();
+			delete f;
 		}
 
 		find_cell(merged.cells, ID($_DFF_N_), false, false, false, false, false, false, dont_use_cells);

passes/techmap/libcache.cc

@@ -0,0 +1,130 @@
+/*
+ *  yosys -- Yosys Open SYnthesis Suite
+ *
+ *  Copyright (C) 2025  Jannis Harder <jix@yosyshq.com> <me@jix.one>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+ #include "kernel/yosys.h"
+ #include "passes/techmap/libparse.h"
+
+ USING_YOSYS_NAMESPACE
+ PRIVATE_NAMESPACE_BEGIN
+
+ struct LibcachePass : public Pass {
+	LibcachePass() : Pass("libcache", "control caching of technology library data parsed from liberty files") { }
+	void help() override
+	{
+		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+		log("\n");
+		log("    libcache {-enable|-disable|-purge} { -all | [path]... }\n");
+		log("\n");
+		log("Controls the default and per path caching of liberty file data.\n");
+		log("\n");
+		log("    -enable    Enable caching.\n");
+		log("    -disable   Disable caching.\n");
+		log("    -purge     Reset cache setting and forget cached data.\n");
+		log("\n");
+		log("This mode takes a list of paths as argument. If no paths are provided, this\n");
+		log("command does nothing. The -all option can be used to change the default cache\n");
+		log("setting for -enable/-disable or to reset and forget about all paths.\n");
+		log("\n");
+		log("By default caching is disabled.\n");
+		log("\n");
+		log("    libcache -list\n");
+		log("\n");
+		log("Displays the current cache settings and cached paths.\n");
+		log("\n");
+	}
+	void execute(std::vector<std::string> args, RTLIL::Design *) override
+	{
+		bool enable = false;
+		bool disable = false;
+		bool purge = false;
+		bool all = false;
+		bool list = false;
+		std::vector<std::string> paths;
+
+		size_t argidx;
+		for (argidx = 1; argidx < args.size(); argidx++) {
+			if (args[argidx] == "-enable") {
+				enable = true;
+				continue;
+			}
+			if (args[argidx] == "-disable") {
+				enable = true;
+				continue;
+			}
+			if (args[argidx] == "-purge") {
+				purge = true;
+				continue;
+			}
+			if (args[argidx] == "-all") {
+				all = true;
+				continue;
+			}
+			if (args[argidx] == "-list") {
+				list = true;
+				continue;
+			}
+			std::string fname = args[argidx];
+			rewrite_filename(fname);
+			paths.push_back(fname);
+			break;
+		}
+		int modes = enable + disable + purge + list;
+		if (modes == 0)
+			log_cmd_error("At least one of -enable, -disable, -purge or -list is required.\n");
+		if (modes > 1)
+			log_cmd_error("Only one of -enable, -disable, -purge or -list may be present.\n");
+
+		if (all && !paths.empty())
+			log_cmd_error("The -all option cannot be combined with a list of paths.\n");
+		if (list && (all || !paths.empty()))
+			log_cmd_error("The -list mode takes no further options.\n");
+		if (!list && !all && paths.empty())
+			log("No paths specified, use -all to %s\n", purge ? "purge all paths" : "change the default setting");
+
+		if (list) {
+			log("Caching is %s by default.\n", LibertyAstCache::instance.cache_by_default ? "enabled" : "disabled");
+			for (auto const &entry : LibertyAstCache::instance.cache_path)
+				log("Caching is %s for `%s'.\n", entry.second ? "enabled" : "disabled", entry.first.c_str());
+			for (auto const &entry : LibertyAstCache::instance.cached)
+				log("Data for `%s' is currently cached.\n", entry.first.c_str());
+		} else if (enable || disable) {
+			if (all) {
+				LibertyAstCache::instance.cache_by_default = enable;
+			} else {
+				for (auto const &path : paths) {
+					LibertyAstCache::instance.cache_path[path] = enable;
+				}
+			}
+		} else if (purge) {
+			if (all) {
+				LibertyAstCache::instance.cached.clear();
+				LibertyAstCache::instance.cache_path.clear();
+			} else {
+				for (auto const &path : paths) {
+					LibertyAstCache::instance.cached.erase(path);
+					LibertyAstCache::instance.cache_path.erase(path);
+				}
+			}
+		} else {
+			log_assert(false);
+		}
+	}
+} LibcachePass;
+
+PRIVATE_NAMESPACE_END

passes/techmap/libparse.cc

@@ -32,6 +32,86 @@
 
 using namespace Yosys;
 
+#ifndef FILTERLIB
+
+LibertyAstCache LibertyAstCache::instance;
+
+std::shared_ptr<const LibertyAst> LibertyAstCache::cached_ast(const std::string &fname)
+{
+	auto it = cached.find(fname);
+	if (it == cached.end())
+		return nullptr;
+	log("Using cached data for liberty file `%s'\n", fname.c_str());
+	return it->second;
+}
+
+void LibertyAstCache::parsed_ast(const std::string &fname, const std::shared_ptr<const LibertyAst> &ast)
+{
+	auto it = cache_path.find(fname);
+	bool should_cache = it == cache_path.end() ? cache_by_default : it->second;
+	if (!should_cache)
+		return;
+	log("Caching data for liberty file `%s'\n", fname.c_str());
+	cached.emplace(fname, ast);
+}
+
+#endif
+
+bool LibertyInputStream::extend_buffer_once()
+{
+	if (eof)
+		return false;
+
+	// To support unget we leave the last already read character in the buffer
+	if (buf_pos > 1) {
+		size_t move_pos = buf_pos - 1;
+		memmove(buffer.data(), buffer.data() + move_pos, buf_end - move_pos);
+		buf_pos -= move_pos;
+		buf_end -= move_pos;
+	}
+
+	const size_t chunk_size = 4096;
+	if (buffer.size() < buf_end + chunk_size) {
+		buffer.resize(buf_end + chunk_size);
+	}
+
+	size_t read_size = f.rdbuf()->sgetn(buffer.data() + buf_end, chunk_size);
+	buf_end += read_size;
+	if (read_size < chunk_size)
+		eof = true;
+	return read_size != 0;
+}
+
+bool LibertyInputStream::extend_buffer_at_least(size_t size) {
+	while (buffered_size() < size) {
+		if (!extend_buffer_once())
+			return false;
+	}
+	return true;
+}
+
+int LibertyInputStream::get_cold()
+{
+	if (buf_pos == buf_end) {
+		if (!extend_buffer_at_least())
+			return EOF;
+	}
+
+	int c = buffer[buf_pos];
+	buf_pos += 1;
+	return c;
+}
+
+int LibertyInputStream::peek_cold(size_t offset)
+{
+	if (buf_pos + offset >= buf_end) {
+		if (!extend_buffer_at_least(offset + 1))
+			return EOF;
+	}
+
+	return buffer[buf_pos + offset];
+}
+
 LibertyAst::~LibertyAst()
 {
 	for (auto child : children)
@@ -237,15 +317,19 @@ int LibertyParser::lexer(std::string &str)
 
 	// search for identifiers, numbers, plus or minus.
 	if (('a' <= c && c <= 'z') || ('A' <= c && c <= 'Z') || ('0' <= c && c <= '9') || c == '_' || c == '-' || c == '+' || c == '.') {
-		str = static_cast<char>(c);
-		while (1) {
-			c = f.get();
+		f.unget();
+		size_t i = 1;
+		while (true) {
+			c = f.peek(i);
 			if (('a' <= c && c <= 'z') || ('A' <= c && c <= 'Z') || ('0' <= c && c <= '9') || c == '_' || c == '-' || c == '+' || c == '.')
-				str += c;
+				i += 1;
 			else
 				break;
 		}
-		f.unget();
+		str.clear();
+		str.append(f.buffered_data(), f.buffered_data() + i);
+		f.consume(i);
+
 		if (str == "+" || str == "-") {
 			/* Single operator is not an identifier */
 			// fprintf(stderr, "LEX: char >>%s<<\n", str.c_str());
@@ -260,23 +344,24 @@ int LibertyParser::lexer(std::string &str)
 	// if it wasn't an identifer, number of array range,
 	// maybe it's a string?
 	if (c == '"') {
-		str = "";
-#ifdef FILTERLIB
-		str += c;
-#endif
-		while (1) {
-			c = f.get();
-			if (c == '\n')
-				line++;
-			if (c == '"') {
-#ifdef FILTERLIB
-				str += c;
-#endif
+		size_t i = 0;
+		while (true) {
+			c = f.peek(i);
+			line += (c == '\n');
+			if (c != '"')
+				i += 1;
+			else
 				break;
-			}
-			str += c;
 		}
-		// fprintf(stderr, "LEX: string >>%s<<\n", str.c_str());
+		str.clear();
+#ifdef FILTERLIB
+		f.unget();
+		str.append(f.buffered_data(), f.buffered_data() + i + 2);
+		f.consume(i + 2);
+#else
+		str.append(f.buffered_data(), f.buffered_data() + i);
+		f.consume(i + 1);
+#endif
 		return 'v';
 	}
 

passes/techmap/libparse.h

@@ -90,12 +90,70 @@ namespace Yosys
 		bool eval(dict<std::string, bool>& values);
 	};
 
+	class LibertyInputStream {
+		std::istream &f;
+		std::vector<char> buffer;
+		size_t buf_pos = 0;
+		size_t buf_end = 0;
+		bool eof = false;
+
+		bool extend_buffer_once();
+		bool extend_buffer_at_least(size_t size = 1);
+
+		YS_COLD int get_cold();
+		YS_COLD int peek_cold(size_t offset);
+
+	public:
+		LibertyInputStream(std::istream &f) : f(f) {}
+
+		size_t buffered_size() { return buf_end - buf_pos; }
+		const char *buffered_data() { return buffer.data() + buf_pos; }
+
+		int get() {
+			if (buf_pos == buf_end)
+				return get_cold();
+			int c = buffer[buf_pos];
+			buf_pos += 1;
+			return c;
+		}
+
+		int peek(size_t offset = 0) {
+			if (buf_pos + offset >= buf_end)
+				return peek_cold(offset);
+			return buffer[buf_pos + offset];
+		}
+
+		void consume(size_t n = 1) {
+			buf_pos += n;
+		}
+
+		void unget() {
+			buf_pos -= 1;
+		}
+	};
+
+#ifndef FILTERLIB
+	class LibertyAstCache {
+		LibertyAstCache() {};
+		~LibertyAstCache() {};
+	public:
+		dict<std::string, std::shared_ptr<const LibertyAst>> cached;
+
+		bool cache_by_default = false;
+		dict<std::string, bool> cache_path;
+
+		std::shared_ptr<const LibertyAst> cached_ast(const std::string &fname);
+		void parsed_ast(const std::string &fname, const std::shared_ptr<const LibertyAst> &ast);
+		static LibertyAstCache instance;
+	};
+#endif
+
 	class LibertyMergedCells;
 	class LibertyParser
 	{
 		friend class LibertyMergedCells;
 	private:
-		std::istream &f;
+		LibertyInputStream f;
 		int line;
 
 		/* lexer return values:
@@ -110,15 +168,29 @@ namespace Yosys
 		void error(const std::string &str) const;
 
 	public:
-		const LibertyAst *ast;
+		std::shared_ptr<const LibertyAst> shared_ast;
+		const LibertyAst *ast = nullptr;
 
-		LibertyParser(std::istream &f) : f(f), line(1), ast(parse()) {}
-		~LibertyParser() { if (ast) delete ast; }
+		LibertyParser(std::istream &f) : f(f), line(1) {
+			shared_ast.reset(parse());
+			ast = shared_ast.get();
+		}
+
+#ifndef FILTERLIB
+		LibertyParser(std::istream &f, const std::string &fname) : f(f), line(1) {
+			shared_ast = LibertyAstCache::instance.cached_ast(fname);
+			if (!shared_ast) {
+				shared_ast.reset(parse());
+				LibertyAstCache::instance.parsed_ast(fname, shared_ast);
+			}
+			ast = shared_ast.get();
+		}
+#endif
 	};
 
 	class LibertyMergedCells
 	{
-		std::vector<const LibertyAst *> asts;
+		std::vector<std::shared_ptr<const LibertyAst>> asts;
 
 	public:
 		std::vector<const LibertyAst *> cells;
@@ -126,10 +198,7 @@ namespace Yosys
 		{
 			if (parser.ast) {
 				const LibertyAst *ast = parser.ast;
-				asts.push_back(ast);
-				// The parser no longer owns its top level ast, but we do.
-				// sketchy zone
-				parser.ast = nullptr;
+				asts.push_back(parser.shared_ast);
 				if (ast->id != "library")
 					parser.error("Top level entity isn't \"library\".\n");
 				for (const LibertyAst *cell : ast->children)
@@ -137,11 +206,6 @@ namespace Yosys
 						cells.push_back(cell);
 			}
 		}
-		~LibertyMergedCells()
-		{
-			for (auto ast : asts)
-				delete ast;
-		}
 	};
 
 }

passes/techmap/maccmap.cc

@@ -403,7 +403,7 @@ struct MaccmapPass : public Pass {
 
 		for (auto mod : design->selected_modules())
 		for (auto cell : mod->selected_cells())
-			if (cell->type == ID($macc)) {
+			if (cell->type.in(ID($macc), ID($macc_v2))) {
 				log("Mapping %s.%s (%s).\n", log_id(mod), log_id(cell), log_id(cell->type));
 				maccmap(mod, cell, unmap_mode);
 				mod->remove(cell);

passes/techmap/techmap.cc

@@ -554,8 +554,8 @@ struct TechmapWorker
 
 							if (extmapper_name == "maccmap") {
 								log("Creating %s with maccmap.\n", log_id(extmapper_module));
-								if (extmapper_cell->type != ID($macc))
-									log_error("The maccmap mapper can only map $macc (not %s) cells!\n", log_id(extmapper_cell->type));
+								if (!extmapper_cell->type.in(ID($macc), ID($macc_v2)))
+									log_error("The maccmap mapper can only map $macc/$macc_v2 (not %s) cells!\n", log_id(extmapper_cell->type));
 								maccmap(extmapper_module, extmapper_cell);
 								extmapper_module->remove(extmapper_cell);
 							}
@@ -600,8 +600,8 @@ struct TechmapWorker
 						}
 
 						if (extmapper_name == "maccmap") {
-							if (cell->type != ID($macc))
-								log_error("The maccmap mapper can only map $macc (not %s) cells!\n", log_id(cell->type));
+							if (!cell->type.in(ID($macc), ID($macc_v2)))
+								log_error("The maccmap mapper can only map $macc/$macc_v2 (not %s) cells!\n", log_id(cell->type));
 							maccmap(module, cell);
 						}
 

techlibs/common/simlib.v

@@ -1207,6 +1207,120 @@ end
 
 endmodule
 
+// --------------------------------------------------------
+//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//-     $macc_v2 (A, B, C, Y)
+//* group arith
+//-
+//- Multiply and add.
+//- This cell represents a generic fused multiply-add operation, it supersedes the
+//- earlier $macc cell.
+//-
+module \$macc_v2 (A, B, C, Y);
+
+parameter NPRODUCTS = 0;
+parameter NADDENDS = 0;
+parameter A_WIDTHS = 16'h0000;
+parameter B_WIDTHS = 16'h0000;
+parameter C_WIDTHS = 16'h0000;
+parameter Y_WIDTH = 0;
+
+parameter PRODUCT_NEGATED = 1'bx;
+parameter ADDEND_NEGATED = 1'bx;
+parameter A_SIGNED = 1'bx;
+parameter B_SIGNED = 1'bx;
+parameter C_SIGNED = 1'bx;
+
+function integer sum_widths1;
+	input [(16*NPRODUCTS)-1:0] widths;
+	integer i;
+	begin
+		sum_widths1 = 0;
+		for (i = 0; i < NPRODUCTS; i++) begin
+			sum_widths1 = sum_widths1 + widths[16*i+:16];
+		end
+	end
+endfunction
+
+function integer sum_widths2;
+	input [(16*NADDENDS)-1:0] widths;
+	integer i;
+	begin
+		sum_widths2 = 0;
+		for (i = 0; i < NADDENDS; i++) begin
+			sum_widths2 = sum_widths2 + widths[16*i+:16];
+		end
+	end
+endfunction
+
+input [sum_widths1(A_WIDTHS)-1:0] A; // concatenation of LHS factors
+input [sum_widths1(B_WIDTHS)-1:0] B; // concatenation of RHS factors
+input [sum_widths2(C_WIDTHS)-1:0] C; // concatenation of summands
+output reg [Y_WIDTH-1:0] Y; // output sum
+
+integer i, j, ai, bi, ci, aw, bw, cw;
+reg [Y_WIDTH-1:0] product;
+reg [Y_WIDTH-1:0] addend, oper_a, oper_b;
+
+always @* begin
+	Y = 0;
+	ai = 0;
+	bi = 0;
+	for (i = 0; i < NPRODUCTS; i = i+1)
+	begin
+		aw = A_WIDTHS[16*i+:16];
+		bw = B_WIDTHS[16*i+:16];
+
+		oper_a = 0;
+		oper_b = 0;
+		for (j = 0; j < Y_WIDTH && j < aw; j = j + 1)
+			oper_a[j] = A[ai + j];
+		for (j = 0; j < Y_WIDTH && j < bw; j = j + 1)
+			oper_b[j] = B[bi + j];
+		// A_SIGNED[i] == B_SIGNED[i] as RTLIL invariant
+		if (A_SIGNED[i] && B_SIGNED[i]) begin
+			for (j = aw; j > 0 && j < Y_WIDTH; j = j + 1)
+				oper_a[j] = oper_a[j - 1];
+			for (j = bw; j > 0 && j < Y_WIDTH; j = j + 1)
+				oper_b[j] = oper_b[j - 1];
+		end
+
+		product = oper_a * oper_b;
+
+		if (PRODUCT_NEGATED[i])
+			Y = Y - product;
+		else
+			Y = Y + product;
+
+		ai = ai + aw;
+		bi = bi + bw;
+	end
+
+	ci = 0;
+	for (i = 0; i < NADDENDS; i = i+1)
+	begin
+		cw = C_WIDTHS[16*i+:16];
+
+		addend = 0;
+		for (j = 0; j < Y_WIDTH && j < cw; j = j + 1)
+			addend[j] = C[ci + j];
+		if (C_SIGNED[i]) begin
+			for (j = cw; j > 0 && j < Y_WIDTH; j = j + 1)
+				addend[j] = addend[j - 1];
+		end
+
+		if (ADDEND_NEGATED[i])
+			Y = Y - addend;
+		else
+			Y = Y + addend;
+
+		ci = ci + cw;
+	end
+end
+
+endmodule
+
 // --------------------------------------------------------
 //* ver 2
 //* title Divider
@@ -2110,10 +2224,10 @@ module \$print (EN, TRG, ARGS);
 parameter PRIORITY = 0;
 
 parameter FORMAT = "";
-parameter ARGS_WIDTH = 0;
+parameter signed ARGS_WIDTH = 0;
 
 parameter TRG_ENABLE = 1;
-parameter TRG_WIDTH = 0;
+parameter signed TRG_WIDTH = 0;
 parameter TRG_POLARITY = 0;
 
 input EN;

techlibs/common/techmap.v

@@ -290,7 +290,7 @@ module _90_alu (A, B, CI, BI, X, Y, CO);
 endmodule
 
 (* techmap_maccmap *)
-(* techmap_celltype = "$macc" *)
+(* techmap_celltype = "$macc $macc_v2" *)
 module _90_macc;
 endmodule
 

techlibs/gatemate/cells_bb.v

@@ -50,14 +50,221 @@ endmodule
 
 (* blackbox *) (* keep *)
 module CC_SERDES #(
-	parameter SERDES_CFG = ""
+	parameter  [4:0] RX_BUF_RESET_TIME = 3,
+	parameter  [4:0] RX_PCS_RESET_TIME = 3,
+	parameter  [4:0] RX_RESET_TIMER_PRESC = 0,
+	parameter  [0:0] RX_RESET_DONE_GATE = 0,
+	parameter  [4:0] RX_CDR_RESET_TIME = 3,
+	parameter  [4:0] RX_EQA_RESET_TIME = 3,
+	parameter  [4:0] RX_PMA_RESET_TIME = 3,
+	parameter  [0:0] RX_WAIT_CDR_LOCK = 1,
+	parameter  [0:0] RX_CALIB_EN = 0,
+	parameter  [0:0] RX_CALIB_OVR = 0,
+	parameter  [3:0] RX_CALIB_VAL = 0,
+	parameter  [2:0] RX_RTERM_VCMSEL = 4,
+	parameter  [0:0] RX_RTERM_PD = 0,
+	parameter  [7:0] RX_EQA_CKP_LF = 8'hA3,
+	parameter  [7:0] RX_EQA_CKP_HF = 8'hA3,
+	parameter  [7:0] RX_EQA_CKP_OFFSET = 8'h01,
+	parameter  [0:0] RX_EN_EQA = 0,
+	parameter  [3:0] RX_EQA_LOCK_CFG = 0,
+	parameter  [4:0] RX_TH_MON1 = 8,
+	parameter  [3:0] RX_EN_EQA_EXT_VALUE = 0,
+	parameter  [4:0] RX_TH_MON2 = 8,
+	parameter  [4:0] RX_TAPW = 8,
+	parameter  [4:0] RX_AFE_OFFSET = 8,
+	parameter [15:0] RX_EQA_CONFIG = 16'h01C0,
+	parameter  [4:0] RX_AFE_PEAK = 16,
+	parameter  [3:0] RX_AFE_GAIN = 8,
+	parameter  [2:0] RX_AFE_VCMSEL = 4,
+	parameter  [7:0] RX_CDR_CKP = 8'hF8,
+	parameter  [7:0] RX_CDR_CKI = 0,
+	parameter  [8:0] RX_CDR_TRANS_TH = 128,
+	parameter  [5:0] RX_CDR_LOCK_CFG = 8'h0B,
+	parameter [14:0] RX_CDR_FREQ_ACC = 0,
+	parameter [15:0] RX_CDR_PHASE_ACC = 0,
+	parameter  [1:0] RX_CDR_SET_ACC_CONFIG = 0,
+	parameter  [0:0] RX_CDR_FORCE_LOCK = 0,
+	parameter  [9:0] RX_ALIGN_MCOMMA_VALUE = 10'h283,
+	parameter  [0:0] RX_MCOMMA_ALIGN_OVR = 0,
+	parameter  [0:0] RX_MCOMMA_ALIGN = 0,
+	parameter  [9:0] RX_ALIGN_PCOMMA_VALUE = 10'h17C,
+	parameter  [0:0] RX_PCOMMA_ALIGN_OVR = 0,
+	parameter  [0:0] RX_PCOMMA_ALIGN = 0,
+	parameter  [1:0] RX_ALIGN_COMMA_WORD = 0,
+	parameter  [9:0] RX_ALIGN_COMMA_ENABLE = 10'h3FF,
+	parameter  [1:0] RX_SLIDE_MODE = 0,
+	parameter  [0:0] RX_COMMA_DETECT_EN_OVR = 0,
+	parameter  [0:0] RX_COMMA_DETECT_EN = 0,
+	parameter  [1:0] RX_SLIDE = 0,
+	parameter  [0:0] RX_EYE_MEAS_EN = 0,
+	parameter [14:0] RX_EYE_MEAS_CFG = 0,
+	parameter  [5:0] RX_MON_PH_OFFSET = 0,
+	parameter  [3:0] RX_EI_BIAS = 0,
+	parameter  [3:0] RX_EI_BW_SEL = 4,
+	parameter  [0:0] RX_EN_EI_DETECTOR_OVR = 0,
+	parameter  [0:0] RX_EN_EI_DETECTOR = 0,
+	parameter  [0:0] RX_DATA_SEL = 0,
+	parameter  [0:0] RX_BUF_BYPASS = 0,
+	parameter  [0:0] RX_CLKCOR_USE = 0,
+	parameter  [5:0] RX_CLKCOR_MIN_LAT = 32,
+	parameter  [5:0] RX_CLKCOR_MAX_LAT = 39,
+	parameter  [9:0] RX_CLKCOR_SEQ_1_0 = 10'h1F7,
+	parameter  [9:0] RX_CLKCOR_SEQ_1_1 = 10'h1F7,
+	parameter  [9:0] RX_CLKCOR_SEQ_1_2 = 10'h1F7,
+	parameter  [9:0] RX_CLKCOR_SEQ_1_3 = 10'h1F7,
+	parameter  [0:0] RX_PMA_LOOPBACK = 0,
+	parameter  [0:0] RX_PCS_LOOPBACK = 0,
+	parameter  [1:0] RX_DATAPATH_SEL = 3,
+	parameter  [0:0] RX_PRBS_OVR = 0,
+	parameter  [2:0] RX_PRBS_SEL = 0,
+	parameter  [0:0] RX_LOOPBACK_OVR = 0,
+	parameter  [0:0] RX_PRBS_CNT_RESET = 0,
+	parameter  [0:0] RX_POWER_DOWN_OVR = 0,
+	parameter  [0:0] RX_POWER_DOWN_N = 0,
+	parameter  [0:0] RX_RESET_OVR = 0,
+	parameter  [0:0] RX_RESET = 0,
+	parameter  [0:0] RX_PMA_RESET_OVR = 0,
+	parameter  [0:0] RX_PMA_RESET = 0,
+	parameter  [0:0] RX_EQA_RESET_OVR = 0,
+	parameter  [0:0] RX_EQA_RESET = 0,
+	parameter  [0:0] RX_CDR_RESET_OVR = 0,
+	parameter  [0:0] RX_CDR_RESET = 0,
+	parameter  [0:0] RX_PCS_RESET_OVR = 0,
+	parameter  [0:0] RX_PCS_RESET = 0,
+	parameter  [0:0] RX_BUF_RESET_OVR = 0,
+	parameter  [0:0] RX_BUF_RESET = 0,
+	parameter  [0:0] RX_POLARITY_OVR = 0,
+	parameter  [0:0] RX_POLARITY = 0,
+	parameter  [0:0] RX_8B10B_EN_OVR = 0,
+	parameter  [0:0] RX_8B10B_EN = 0,
+	parameter  [7:0] RX_8B10B_BYPASS = 0,
+	parameter  [0:0] RX_BYTE_REALIGN = 0,
+	parameter  [0:0] RX_DBG_EN = 0,
+	parameter  [1:0] RX_DBG_SEL = 0,
+	parameter  [0:0] RX_DBG_MODE = 0,
+	parameter  [5:0] RX_DBG_SRAM_DELAY = 6'h05,
+	parameter  [9:0] RX_DBG_ADDR = 0,
+	parameter  [0:0] RX_DBG_RE = 0,
+	parameter  [0:0] RX_DBG_WE = 0,
+	parameter [19:0] RX_DBG_DATA = 0,
+	parameter  [4:0] TX_SEL_PRE = 0,
+	parameter  [4:0] TX_SEL_POST = 0,
+	parameter  [4:0] TX_AMP = 15,
+	parameter  [4:0] TX_BRANCH_EN_PRE = 0,
+	parameter  [5:0] TX_BRANCH_EN_MAIN = 6'h3F,
+	parameter  [4:0] TX_BRANCH_EN_POST = 0,
+	parameter  [2:0] TX_TAIL_CASCODE = 4,
+	parameter  [6:0] TX_DC_ENABLE = 63,
+	parameter  [4:0] TX_DC_OFFSET = 0,
+	parameter  [4:0] TX_CM_RAISE = 0,
+	parameter  [4:0] TX_CM_THRESHOLD_0 = 14,
+	parameter  [4:0] TX_CM_THRESHOLD_1 = 16,
+	parameter  [4:0] TX_SEL_PRE_EI = 0,
+	parameter  [4:0] TX_SEL_POST_EI = 0,
+	parameter  [4:0] TX_AMP_EI = 15,
+	parameter  [4:0] TX_BRANCH_EN_PRE_EI = 0,
+	parameter  [5:0] TX_BRANCH_EN_MAIN_EI = 6'h3F,
+	parameter  [4:0] TX_BRANCH_EN_POST_EI = 0,
+	parameter  [2:0] TX_TAIL_CASCODE_EI = 4,
+	parameter  [6:0] TX_DC_ENABLE_EI = 63,
+	parameter  [4:0] TX_DC_OFFSET_EI = 0,
+	parameter  [4:0] TX_CM_RAISE_EI = 0,
+	parameter  [4:0] TX_CM_THRESHOLD_0_EI = 14,
+	parameter  [4:0] TX_CM_THRESHOLD_1_EI = 16,
+	parameter  [4:0] TX_SEL_PRE_RXDET = 0,
+	parameter  [4:0] TX_SEL_POST_RXDET = 0,
+	parameter  [4:0] TX_AMP_RXDET = 15,
+	parameter  [4:0] TX_BRANCH_EN_PRE_RXDET = 0,
+	parameter  [5:0] TX_BRANCH_EN_MAIN_RXDET = 6'h3F,
+	parameter  [4:0] TX_BRANCH_EN_POST_RXDET = 0,
+	parameter  [2:0] TX_TAIL_CASCODE_RXDET = 4,
+	parameter  [6:0] TX_DC_ENABLE_RXDET = 63,
+	parameter  [4:0] TX_DC_OFFSET_RXDET = 0,
+	parameter  [4:0] TX_CM_RAISE_RXDET = 0,
+	parameter  [4:0] TX_CM_THRESHOLD_0_RXDET = 14,
+	parameter  [4:0] TX_CM_THRESHOLD_1_RXDET = 16,
+	parameter  [0:0] TX_CALIB_EN = 0,
+	parameter  [0:0] TX_CALIB_OVR = 0,
+	parameter  [3:0] TX_CALIB_VAL = 0,
+	parameter  [7:0] TX_CM_REG_KI = 8'h80,
+	parameter  [0:0] TX_CM_SAR_EN = 0,
+	parameter  [0:0] TX_CM_REG_EN = 1,
+	parameter  [4:0] TX_PMA_RESET_TIME = 3,
+	parameter  [4:0] TX_PCS_RESET_TIME = 3,
+	parameter  [0:0] TX_PCS_RESET_OVR = 0,
+	parameter  [0:0] TX_PCS_RESET = 0,
+	parameter  [0:0] TX_PMA_RESET_OVR = 0,
+	parameter  [0:0] TX_PMA_RESET = 0,
+	parameter  [0:0] TX_RESET_OVR = 0,
+	parameter  [0:0] TX_RESET = 0,
+	parameter  [1:0] TX_PMA_LOOPBACK = 0,
+	parameter  [0:0] TX_PCS_LOOPBACK = 0,
+	parameter  [1:0] TX_DATAPATH_SEL = 3,
+	parameter  [0:0] TX_PRBS_OVR = 0,
+	parameter  [2:0] TX_PRBS_SEL = 0,
+	parameter  [0:0] TX_PRBS_FORCE_ERR = 0,
+	parameter  [0:0] TX_LOOPBACK_OVR = 0,
+	parameter  [0:0] TX_POWER_DOWN_OVR = 0,
+	parameter  [0:0] TX_POWER_DOWN_N = 0,
+	parameter  [0:0] TX_ELEC_IDLE_OVR = 0,
+	parameter  [0:0] TX_ELEC_IDLE = 0,
+	parameter  [0:0] TX_DETECT_RX_OVR = 0,
+	parameter  [0:0] TX_DETECT_RX = 0,
+	parameter  [0:0] TX_POLARITY_OVR = 0,
+	parameter  [0:0] TX_POLARITY = 0,
+	parameter  [0:0] TX_8B10B_EN_OVR = 0,
+	parameter  [0:0] TX_8B10B_EN = 0,
+	parameter  [0:0] TX_DATA_OVR = 0,
+	parameter  [2:0] TX_DATA_CNT = 0,
+	parameter  [0:0] TX_DATA_VALID = 0,
+	parameter  [0:0] PLL_EN_ADPLL_CTRL = 0,
+	parameter  [0:0] PLL_CONFIG_SEL = 0,
+	parameter  [0:0] PLL_SET_OP_LOCK = 0,
+	parameter  [0:0] PLL_ENFORCE_LOCK = 0,
+	parameter  [0:0] PLL_DISABLE_LOCK = 0,
+	parameter  [0:0] PLL_LOCK_WINDOW = 1,
+	parameter  [0:0] PLL_FAST_LOCK = 1,
+	parameter  [0:0] PLL_SYNC_BYPASS = 0,
+	parameter  [0:0] PLL_PFD_SELECT = 0,
+	parameter  [0:0] PLL_REF_BYPASS = 0,
+	parameter  [0:0] PLL_REF_SEL = 0,
+	parameter  [0:0] PLL_REF_RTERM = 1,
+	parameter  [5:0] PLL_FCNTRL = 58,
+	parameter  [5:0] PLL_MAIN_DIVSEL = 27,
+	parameter  [1:0] PLL_OUT_DIVSEL = 0,
+	parameter  [4:0] PLL_CI = 3,
+	parameter  [9:0] PLL_CP = 80,
+	parameter  [3:0] PLL_AO = 0,
+	parameter  [2:0] PLL_SCAP = 0,
+	parameter  [1:0] PLL_FILTER_SHIFT = 2,
+	parameter  [2:0] PLL_SAR_LIMIT = 2,
+	parameter [10:0] PLL_FT = 512,
+	parameter  [0:0] PLL_OPEN_LOOP = 0,
+	parameter  [0:0] PLL_SCAP_AUTO_CAL = 1,
+	parameter  [2:0] PLL_BISC_MODE = 4,
+	parameter  [3:0] PLL_BISC_TIMER_MAX = 15,
+	parameter  [0:0] PLL_BISC_OPT_DET_IND = 0,
+	parameter  [0:0] PLL_BISC_PFD_SEL = 0,
+	parameter  [0:0] PLL_BISC_DLY_DIR = 0,
+	parameter  [2:0] PLL_BISC_COR_DLY = 1,
+	parameter  [0:0] PLL_BISC_CAL_SIGN = 0,
+	parameter  [0:0] PLL_BISC_CAL_AUTO = 1,
+	parameter  [4:0] PLL_BISC_CP_MIN = 4,
+	parameter  [4:0] PLL_BISC_CP_MAX = 18,
+	parameter  [4:0] PLL_BISC_CP_START = 12,
+	parameter  [4:0] PLL_BISC_DLY_PFD_MON_REF = 0,
+	parameter  [4:0] PLL_BISC_DLY_PFD_MON_DIV = 2,
+	parameter  [0:0] SERDES_ENABLE = 0,
+	parameter  [0:0] SERDES_AUTO_INIT = 0,
+	parameter  [0:0] SERDES_TESTMODE = 0
 )(
 	input [63:0] TX_DATA_I,
 	input TX_RESET_I,
 	input TX_PCS_RESET_I,
 	input TX_PMA_RESET_I,
 	input PLL_RESET_I,
-	input TX_POWERDOWN_N_I,
+	input TX_POWER_DOWN_N_I,
 	input TX_POLARITY_I,
 	input [2:0] TX_PRBS_SEL_I,
 	input TX_PRBS_FORCE_ERR_I,
@@ -69,15 +276,15 @@ module CC_SERDES #(
 	input TX_ELEC_IDLE_I,
 	input TX_DETECT_RX_I,
 	input [2:0] LOOPBACK_I,
-	input CLK_CORE_TX_I,
-	input CLK_CORE_RX_I,
+	input TX_CLK_I,
+	input RX_CLK_I,
 	input RX_RESET_I,
 	input RX_PMA_RESET_I,
 	input RX_EQA_RESET_I,
 	input RX_CDR_RESET_I,
 	input RX_PCS_RESET_I,
 	input RX_BUF_RESET_I,
-	input RX_POWERDOWN_N_I,
+	input RX_POWER_DOWN_N_I,
 	input RX_POLARITY_I,
 	input [2:0] RX_PRBS_SEL_I,
 	input RX_PRBS_CNT_RESET_I,
@@ -88,7 +295,7 @@ module CC_SERDES #(
 	input RX_SLIDE_I,
 	input RX_MCOMMA_ALIGN_I,
 	input RX_PCOMMA_ALIGN_I,
-	input CLK_REG_I,
+	input REGFILE_CLK_I,
 	input REGFILE_WE_I,
 	input REGFILE_EN_I,
 	input [7:0] REGFILE_ADDR_I,
@@ -99,18 +306,18 @@ module CC_SERDES #(
 	output [7:0] RX_CHAR_IS_COMMA_O,
 	output [7:0] RX_CHAR_IS_K_O,
 	output [7:0] RX_DISP_ERR_O,
-	output RX_DETECT_DONE_O,
-	output RX_PRESENT_O,
+	output TX_DETECT_RX_DONE_O,
+	output TX_DETECT_RX_PRESENT_O,
 	output TX_BUF_ERR_O,
-	output TX_RESETDONE_O,
+	output TX_RESET_DONE_O,
 	output RX_PRBS_ERR_O,
 	output RX_BUF_ERR_O,
 	output RX_BYTE_IS_ALIGNED_O,
 	output RX_BYTE_REALIGN_O,
-	output RX_RESETDONE_O,
+	output RX_RESET_DONE_O,
 	output RX_EI_EN_O,
-	output CLK_CORE_RX_O,
-	output CLK_CORE_PLL_O,
+	output RX_CLK_O,
+	output PLL_CLK_O,
 	output [15:0] REGFILE_DO_O,
 	output REGFILE_RDY_O
 );

techlibs/gowin/cells_sim.v

@@ -1005,7 +1005,7 @@ always @* begin
 			C = I0;
 		end
 		MULT: begin
-			S = I0 & I1;
+			S = (I0 & I1) ^ I3;
 			C = I0 & I1;
 		end
 	endcase

techlibs/gowin/cells_xtra.py

@@ -13,7 +13,8 @@ class State(Enum):
     IN_MODULE = auto()
     IN_PARAMETER = auto()
 
-_skip = { 'ALU', 'BANDGAP', 'DFF', 'DFFC', 'DFFCE', 'DFFE', 'DFFN', 'DFFNC', 'DFFNCE',
+_skip = { # These are already described, no need to extract them from the vendor files
+          'ALU', 'BANDGAP', 'DFF', 'DFFC', 'DFFCE', 'DFFE', 'DFFN', 'DFFNC', 'DFFNCE',
           'DFFNE', 'DFFNP', 'DFFNPE', 'DFFNR', 'DFFNRE', 'DFFNS', 'DFFNSE',
           'DFFP', 'DFFPE', 'DFFR', 'DFFRE', 'DFFS', 'DFFSE', 'DP', 'DPX9',
           'ELVDS_OBUF', 'GND', 'GSR', 'IBUF', 'IDDR', 'IDDRC', 'IDES10',
@@ -23,7 +24,13 @@ _skip = { 'ALU', 'BANDGAP', 'DFF', 'DFFC', 'DFFCE', 'DFFE', 'DFFN', 'DFFNC', 'DF
           'OSCO', 'OSCW', 'OSCZ', 'OSER10', 'OSER16', 'OSER10', 'OSER4',
           'OSER8', 'OVIDEO', 'PLLVR', 'RAM16S1', 'RAM16S2', 'RAM16S4',
           'RAM16SDP1', 'RAM16SDP2', 'RAM16SDP4', 'rPLL', 'SDP',
-          'SDPX9', 'SP', 'SPX9', 'TBUF', 'TLVDS_OBUF', 'VCC', 'DCS', 'EMCU'
+          'SDPX9', 'SP', 'SPX9', 'TBUF', 'TLVDS_OBUF', 'VCC', 'DCS', 'EMCU',
+          # These are not planned for implementation
+          'MUX2_MUX8', 'MUX2_MUX16', 'MUX2_MUX32', 'MUX4', 'MUX8', 'MUX16',
+          'MUX32', 'DL', 'DLE', 'DLC', 'DLCE', 'DLP', 'DLPE', 'DLN', 'DLNE',
+          'DLNC', 'DLNCE', 'DLNP', 'DLNPE', 'rSDP', 'rSDPX9', 'rROM', 'rROMX9',
+          'TLVDS_OEN_BK', 'DLL', 'DCC', 'I3C', 'IODELAYA', 'IODELAYC', 'IODELAYB',
+          'SPMI', 'PLLO', 'DCCG', 'MIPI_DPHY_RX', 'CLKDIVG', 'PWRGRD', 'FLASH96KA',
         }
 def xtract_cells_decl(dir, fout):
     fname = os.path.join(dir, 'prim_sim.v')

techlibs/gowin/cells_xtra_gw1n.v

@@ -1,53 +1,6 @@
 // Created by cells_xtra.py
 
 
-module MUX2_MUX8 (...);
-input I0,I1;
-input S0;
-output O;
-endmodule
-
-
-module MUX2_MUX16 (...);
-input I0,I1;
-input S0;
-output O;
-endmodule
-
-
-module MUX2_MUX32 (...);
-input I0,I1;
-input S0;
-output O;
-endmodule
-
-
-module MUX4 (...);
-input I0, I1, I2, I3;
-input S0, S1;
-output O;
-endmodule
-
-
-module MUX8 (...);
-input I0, I1, I2, I3, I4, I5, I6, I7;
-input S0, S1, S2;
-output O;
-endmodule
-
-
-module MUX16 (...);
-input I0, I1, I2, I3, I4, I5, I6, I7, I8, I9, I10, I11, I12, I13, I14, I15;
-input S0, S1, S2, S3;
-output O;
-endmodule
-
-module MUX32 (...);
-input I0, I1, I2, I3, I4, I5, I6, I7, I8, I9, I10, I11, I12, I13, I14, I15, I16, I17, I18, I19, I20, I21, I22, I23, I24, I25, I26, I27, I28, I29, I30, I31;
-input S0, S1, S2, S3, S4;
-output O;
-endmodule
-
 module LUT5 (...);
 parameter INIT = 32'h00000000;
 input I0, I1, I2, I3, I4;
@@ -76,90 +29,6 @@ output F;
 endmodule
 
 
-module DL (...);
-input D, G;
-output Q;
-parameter INIT = 1'b0;
-endmodule
-
-
-module DLE (...);
-input D, G, CE;
-output Q;
-parameter INIT = 1'b0;
-endmodule
-
-
-module DLC (...);
-input D, G, CLEAR;
-output Q;
-parameter INIT = 1'b0;
-endmodule
-
-
-module DLCE (...);
-input D, G, CLEAR, CE;
-output Q;
-parameter INIT = 1'b0;
-endmodule
-
-
-module DLP (...);
-input D, G, PRESET;
-output Q;
-parameter INIT = 1'b1;
-endmodule
-
-
-module DLPE (...);
-input D, G, PRESET, CE;
-output Q;
-parameter INIT = 1'b1;
-endmodule
-
-
-module DLN (...);
-input D, G;
-output Q;
-parameter INIT = 1'b0;
-endmodule
-
-
-module DLNE (...);
-input D, G, CE;
-output Q;
-parameter INIT = 1'b0;
-endmodule
-
-
-module DLNC (...);
-input D, G, CLEAR;
-output Q;
-parameter INIT = 1'b0;
-endmodule
-
-
-module DLNCE (...);
-input D, G, CLEAR, CE;
-output Q;
-parameter INIT = 1'b0;
-endmodule
-
-
-module DLNP (...);
-input D, G, PRESET;
-output Q;
-parameter INIT = 1'b1;
-endmodule
-
-
-module DLNPE (...);
-input D, G, PRESET, CE;
-output Q;
-parameter INIT = 1'b1;
-endmodule
-
-
 module INV (...);
 input  I;
 output O;
@@ -351,322 +220,6 @@ output [35:0] DO;
 endmodule
 
 
-module rSDP (...);
-parameter READ_MODE = 1'b0; 
-parameter BIT_WIDTH_0 = 32; 
-parameter BIT_WIDTH_1 = 32; 
-parameter BLK_SEL = 3'b000;
-parameter RESET_MODE = "SYNC"; 
-parameter INIT_RAM_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-input CLKA, CEA, CLKB, CEB;
-input OCE; 
-input RESETA, RESETB; 
-input [13:0] ADA, ADB;
-input [31:0] DI;
-input [2:0] BLKSEL;
-output [31:0] DO;
-endmodule
-
-
-module rSDPX9 (...);
-parameter READ_MODE = 1'b0; 
-parameter BIT_WIDTH_0 = 36; 
-parameter BIT_WIDTH_1 = 36; 
-parameter BLK_SEL = 3'b000;
-parameter RESET_MODE = "SYNC"; 
-parameter INIT_RAM_00 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; 
-parameter INIT_RAM_01 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_02 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_03 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_04 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_05 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_06 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_07 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_08 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_09 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_0A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_0B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_0C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_0D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_0E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_0F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_10 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_11 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_12 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_13 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_14 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_15 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_16 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_17 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_18 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_19 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_1A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_1B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_1C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_1D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_1E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_1F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_20 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_21 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_22 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_23 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_24 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_25 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_26 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_27 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_28 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_29 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_2A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_2B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_2C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_2D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_2E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_2F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_30 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_31 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_32 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_33 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_34 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_35 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_36 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_37 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_38 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_39 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_3A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_3B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_3C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_3D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_3E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_3F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-input CLKA, CEA, CLKB, CEB;
-input OCE; 
-input RESETA, RESETB; 
-input [13:0] ADA, ADB;
-input [2:0] BLKSEL;
-input [35:0] DI;
-output [35:0] DO;
-endmodule
-
-
-module rROM (...);
-parameter READ_MODE = 1'b0; 
-parameter BIT_WIDTH = 32; 
-parameter BLK_SEL = 3'b000;
-parameter RESET_MODE = "SYNC"; 
-parameter INIT_RAM_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-input CLK, CE;
-input OCE; 
-input RESET; 
-input [13:0] AD;
-input [2:0] BLKSEL;
-output [31:0] DO;
-endmodule
-
-
-module rROMX9 (...);
-parameter READ_MODE = 1'b0; 
-parameter BIT_WIDTH = 36; 
-parameter BLK_SEL = 3'b000;
-parameter RESET_MODE = "SYNC"; 
-parameter INIT_RAM_00 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; 
-parameter INIT_RAM_01 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_02 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_03 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_04 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_05 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_06 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_07 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_08 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_09 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_0A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_0B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_0C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_0D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_0E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_0F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_10 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_11 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_12 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_13 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_14 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_15 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_16 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_17 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_18 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_19 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_1A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_1B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_1C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_1D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_1E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_1F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_20 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_21 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_22 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_23 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_24 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_25 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_26 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_27 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_28 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_29 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_2A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_2B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_2C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_2D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_2E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_2F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_30 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_31 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_32 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_33 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_34 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_35 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_36 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_37 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_38 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_39 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_3A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_3B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_3C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_3D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_3E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_3F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-input CLK, CE;
-input OCE; 
-input RESET; 
-input [13:0] AD;
-input [2:0] BLKSEL;
-output [35:0] DO;
-endmodule
-
-
 module pROM (...);
 parameter READ_MODE = 1'b0; 
 parameter BIT_WIDTH = 32; 
@@ -1476,11 +1029,6 @@ inout IO;
 input  I, MODESEL;
 endmodule
 
-module TLVDS_OEN_BK (...);
-input OEN;
-parameter OEN_BANK = "0"; 
-endmodule
-
 module CLKDIV (...);
 input HCLKIN;
 input RESETN;
@@ -1495,19 +1043,6 @@ input CLKIN,CE;
 output CLKOUT;
 endmodule
 
-module DLL (...);
-input CLKIN;
-input STOP;
-input UPDNCNTL;
-input RESET;
-output [7:0]STEP;
-output LOCK;
-parameter DLL_FORCE = 0;
-parameter CODESCAL="000";
-parameter SCAL_EN="true";
-parameter DIV_SEL = 1'b0; 
-endmodule
-
 module DLLDLY (...);
 input CLKIN;
 input [7:0] DLLSTEP;
@@ -1586,13 +1121,6 @@ input HCLKIN, RESETN;
 output CLKOUT;
 endmodule
 
-module DCC (...);
-output CLKOUT;
-input CLKIN;
-parameter DCC_EN = 1'b1; 
-parameter FCLKIN = 50.0;
-endmodule
-
 module DHCENC (...);
 input CLKIN, CE;
 output CLKOUT, CLKOUTN;
@@ -1642,252 +1170,3 @@ parameter IDLE    =  4'd0,
 		  RD_S1   =  4'd11,
 		  RD_S2   =  4'd12;		  
 endmodule
-
-module I3C (...);
-parameter ADDRESS = 7'b0000000;
-input 	LGYS, CMS, ACS, AAS, STOPS, STRTS;
-output 	LGYO, CMO, ACO, AAO, SIO, STOPO, STRTO;
-input 	LGYC, CMC, ACC, AAC, SIC, STOPC, STRTC;
-input	STRTHDS, SENDAHS, SENDALS, ACKHS;
-input	ACKLS, STOPSUS, STOPHDS, SENDDHS;
-input	SENDDLS, RECVDHS, RECVDLS, ADDRS;
-output	PARITYERROR;
-input 	[7:0] DI;
-output 	[7:0] DOBUF;
-output 	[7:0] DO;
-output 	[7:0] STATE;
-input	SDAI, SCLI;
-output	SDAO, SCLO;
-output	SDAOEN, SCLOEN;
-output	SDAPULLO, SCLPULLO;
-output	SDAPULLOEN, SCLPULLOEN;
-input 	CE, RESET, CLK;
-endmodule
-
-module IODELAYA (...);
-parameter C_STATIC_DLY = 0; 
-input DI;
-input  SDTAP;
-input  SETN;
-input  VALUE;
-output DF;
-output DO;
-endmodule
-
-module IODELAYC (...);
-parameter C_STATIC_DLY = 0; 
-parameter DYN_DA_SEL = "false"; 
-parameter DA_SEL = 2'b00;
-input DI;
-input  SDTAP;
-input  SETN;
-input  VALUE;
-input [1:0] DASEL;
-input [1:0] DAADJ;
-output DF;
-output DO;
-output DAO;
-endmodule
-
-
-module SPMI (...);
-parameter FUNCTION_CTRL = 7'b0000000; 
-parameter MSID_CLKSEL = 7'b0000000;
-parameter RESPOND_DELAY = 4'b0000;
-parameter SCLK_NORMAL_PERIOD = 7'b0000000;
-parameter SCLK_LOW_PERIOD = 7'b0000000;
-parameter CLK_FREQ = 7'b0000000;
-parameter SHUTDOWN_BY_ENABLE = 1'b0; 
-input	CLKEXT, ENEXT;
-inout	SDATA, 	SCLK;
-input 	CLK, CE, RESETN, LOCRESET;
-input 	PA, SA, CA;
-input	[3:0] 	ADDRI;
-input	[7:0] 	DATAI;
-output 	[3:0] 	ADDRO;
-output 	[7:0] 	DATAO;
-output 	[15:0] 	STATE;
-output	[3:0]	CMD;
-endmodule
-
-module IODELAYB (...);
-parameter C_STATIC_DLY = 0; 
-parameter DELAY_MUX = 2'b00; 
-parameter DA_SEL = 2'b00;
-input DI;
-input  SDTAP;
-input  SETN;
-input  VALUE;
-input [1:0] DAADJ;
-output DF;
-output DO;
-output DAO;
-endmodule
-
-
-module PLLO (...);
-input CLKIN;
-input CLKFB;
-input RESET;
-input RESET_P;
-input RESET_I;
-input RESET_S;
-input [5:0] FBDSEL;
-input [5:0] IDSEL;
-input [6:0] ODSELA;
-input [6:0] ODSELB;
-input [6:0] ODSELC;
-input [6:0] ODSELD;
-input [3:0] DTA;
-input [3:0] DTB;
-input [4:0] ICPSEL;
-input [2:0] LPFRES;
-input [1:0] PSSEL;
-input PSDIR;
-input PSPULSE;
-input ENCLKA;
-input ENCLKB;
-input ENCLKC;
-input ENCLKD;
-output LOCK;
-output CLKOUTA;
-output CLKOUTB;
-output CLKOUTC;
-output CLKOUTD;
-parameter FCLKIN = "100.0"; 
-parameter DYN_IDIV_SEL= "FALSE";
-parameter IDIV_SEL = 0; 
-parameter DYN_FBDIV_SEL= "FALSE";
-parameter FBDIV_SEL = 0; 
-parameter DYN_ODIVA_SEL= "FALSE";
-parameter ODIVA_SEL = 6; 
-parameter DYN_ODIVB_SEL= "FALSE";
-parameter ODIVB_SEL = 6; 
-parameter DYN_ODIVC_SEL= "FALSE";
-parameter ODIVC_SEL = 6; 
-parameter DYN_ODIVD_SEL= "FALSE";
-parameter ODIVD_SEL = 6; 
-parameter CLKOUTA_EN = "TRUE";
-parameter CLKOUTB_EN = "TRUE";
-parameter CLKOUTC_EN = "TRUE";
-parameter CLKOUTD_EN = "TRUE";
-parameter DYN_DTA_SEL = "FALSE"; 
-parameter DYN_DTB_SEL = "FALSE"; 
-parameter CLKOUTA_DT_DIR = 1'b1; 
-parameter CLKOUTB_DT_DIR = 1'b1; 
-parameter CLKOUTA_DT_STEP = 0; 
-parameter CLKOUTB_DT_STEP = 0; 
-parameter CLKA_IN_SEL = 2'b00;
-parameter CLKA_OUT_SEL = 1'b0;
-parameter CLKB_IN_SEL = 2'b00;
-parameter CLKB_OUT_SEL = 1'b0;
-parameter CLKC_IN_SEL = 2'b00;
-parameter CLKC_OUT_SEL = 1'b0;
-parameter CLKD_IN_SEL = 2'b00;
-parameter CLKD_OUT_SEL = 1'b0;
-parameter CLKFB_SEL = "INTERNAL"; 
-parameter DYN_DPA_EN = "FALSE";
-parameter DYN_PSB_SEL = "FALSE";
-parameter DYN_PSC_SEL = "FALSE";
-parameter DYN_PSD_SEL = "FALSE";
-parameter PSB_COARSE = 1;
-parameter PSB_FINE = 0;
-parameter PSC_COARSE = 1;
-parameter PSC_FINE = 0;
-parameter PSD_COARSE = 1;
-parameter PSD_FINE = 0;
-parameter DTMS_ENB = "FALSE";
-parameter DTMS_ENC = "FALSE";
-parameter DTMS_END = "FALSE";
-parameter RESET_I_EN = "FALSE";
-parameter RESET_S_EN =  "FALSE";
-parameter DYN_ICP_SEL= "FALSE";
-parameter ICP_SEL = 5'bXXXXX;
-parameter DYN_RES_SEL= "FALSE";
-parameter LPR_REF = 7'bXXXXXXX;
-endmodule
-
-module DCCG (...);
-output CLKOUT;
-input CLKIN;
-parameter DCC_MODE = 2'b00; 
-parameter FCLKIN = 50.0;
-endmodule
-
-module FLASH96KA (...);
-input[5:0]XADR;
-input[5:0]YADR;
-input XE,YE,SE;
-input ERASE,PROG,NVSTR;
-input [31:0] DIN;
-input SLEEP;
-output reg [31:0] DOUT;
-parameter IDLE    =  4'd0,
-          ERA_S1  =  4'd1,
-		  ERA_S2  =  4'd2,
-		  ERA_S3  =  4'd3,
-		  ERA_S4  =  4'd4,
-		  ERA_S5  =  4'd5,
-		  PRO_S1  =  4'd6,
-		  PRO_S2  =  4'd7,
-		  PRO_S3  =  4'd8,
-		  PRO_S4  =  4'd9,
-		  PRO_S5  =  4'd10,
-		  RD_S1   =  4'd11,
-		  RD_S2   =  4'd12;		  
-endmodule
-
-module MIPI_DPHY_RX (...);
-output [15:0] D0LN_HSRXD, D1LN_HSRXD, D2LN_HSRXD, D3LN_HSRXD;
-output D0LN_HSRXD_VLD,D1LN_HSRXD_VLD,D2LN_HSRXD_VLD,D3LN_HSRXD_VLD;
-output DI_LPRX0_N, DI_LPRX0_P, DI_LPRX1_N, DI_LPRX1_P, DI_LPRX2_N, DI_LPRX2_P, DI_LPRX3_N, DI_LPRX3_P;
-output DI_LPRXCK_N, DI_LPRXCK_P;
-output RX_CLK_O;          
-output DESKEW_ERROR;      
-inout  CK_N, CK_P, RX0_N, RX0_P, RX1_N, RX1_P, RX2_N, RX2_P, RX3_N, RX3_P;
-input LPRX_EN_CK, LPRX_EN_D0, LPRX_EN_D1, LPRX_EN_D2, LPRX_EN_D3;
-input HSRX_ODTEN_CK, HSRX_ODTEN_D0,  HSRX_ODTEN_D1, HSRX_ODTEN_D2, HSRX_ODTEN_D3;
-input D0LN_HSRX_DREN,  D1LN_HSRX_DREN, D2LN_HSRX_DREN, D3LN_HSRX_DREN;
-input HSRX_EN_CK;         
-input HS_8BIT_MODE;       
-input RX_CLK_1X;          
-input RX_INVERT;          
-input LALIGN_EN;          
-input WALIGN_BY;          
-input DO_LPTX0_N, DO_LPTX0_P, DO_LPTX1_N, DO_LPTX1_P, DO_LPTX2_N, DO_LPTX2_P, DO_LPTX3_N, DO_LPTX3_P;
-input DO_LPTXCK_N, DO_LPTXCK_P;
-input LPTX_EN_CK, LPTX_EN_D0, LPTX_EN_D1, LPTX_EN_D2, LPTX_EN_D3;
-input BYTE_LENDIAN;       
-input HSRX_STOP;          
-input LPRX_ULP_LN0, LPRX_ULP_LN1, LPRX_ULP_LN2, LPRX_ULP_LN3, LPRX_ULP_CK;
-input PWRON;              
-input RESET;              
-input [2:0] DESKEW_LNSEL; 
-input [7:0] DESKEW_MTH;   
-input [6:0] DESKEW_OWVAL; 
-input DESKEW_REQ;         
-input DRST_N;             
-input ONE_BYTE0_MATCH;    
-input WORD_LENDIAN;       
-input [2:0] FIFO_RD_STD;  
-parameter ALIGN_BYTE = 8'b10111000;
-parameter MIPI_LANE0_EN = 1'b0;
-parameter MIPI_LANE1_EN = 1'b0;
-parameter MIPI_LANE2_EN = 1'b0;
-parameter MIPI_LANE3_EN = 1'b0;
-parameter MIPI_CK_EN = 1'b1;
-parameter SYNC_CLK_SEL = 1'b0;
-endmodule
-
-module CLKDIVG (...);
-input CLKIN;
-input RESETN;
-input CALIB;
-output CLKOUT;
-parameter DIV_MODE = "2"; 
-parameter GSREN = "false"; 
-endmodule
-
-module PWRGRD (...);
-input PDEN; 
-endmodule

techlibs/gowin/cells_xtra_gw2a.v

@@ -1,53 +1,6 @@
 // Created by cells_xtra.py
 
 
-module MUX2_MUX8 (...);
-input I0,I1;
-input S0;
-output O;
-endmodule
-
-
-module MUX2_MUX16 (...);
-input I0,I1;
-input S0;
-output O;
-endmodule
-
-
-module MUX2_MUX32 (...);
-input I0,I1;
-input S0;
-output O;
-endmodule
-
-
-module MUX4 (...);
-input I0, I1, I2, I3;
-input S0, S1;
-output O;
-endmodule
-
-
-module MUX8 (...);
-input I0, I1, I2, I3, I4, I5, I6, I7;
-input S0, S1, S2;
-output O;
-endmodule
-
-
-module MUX16 (...);
-input I0, I1, I2, I3, I4, I5, I6, I7, I8, I9, I10, I11, I12, I13, I14, I15;
-input S0, S1, S2, S3;
-output O;
-endmodule
-
-module MUX32 (...);
-input I0, I1, I2, I3, I4, I5, I6, I7, I8, I9, I10, I11, I12, I13, I14, I15, I16, I17, I18, I19, I20, I21, I22, I23, I24, I25, I26, I27, I28, I29, I30, I31;
-input S0, S1, S2, S3, S4;
-output O;
-endmodule
-
 module LUT5 (...);
 parameter INIT = 32'h00000000;
 input I0, I1, I2, I3, I4;
@@ -76,90 +29,6 @@ output F;
 endmodule
 
 
-module DL (...);
-input D, G;
-output Q;
-parameter INIT = 1'b0;
-endmodule
-
-
-module DLE (...);
-input D, G, CE;
-output Q;
-parameter INIT = 1'b0;
-endmodule
-
-
-module DLC (...);
-input D, G, CLEAR;
-output Q;
-parameter INIT = 1'b0;
-endmodule
-
-
-module DLCE (...);
-input D, G, CLEAR, CE;
-output Q;
-parameter INIT = 1'b0;
-endmodule
-
-
-module DLP (...);
-input D, G, PRESET;
-output Q;
-parameter INIT = 1'b1;
-endmodule
-
-
-module DLPE (...);
-input D, G, PRESET, CE;
-output Q;
-parameter INIT = 1'b1;
-endmodule
-
-
-module DLN (...);
-input D, G;
-output Q;
-parameter INIT = 1'b0;
-endmodule
-
-
-module DLNE (...);
-input D, G, CE;
-output Q;
-parameter INIT = 1'b0;
-endmodule
-
-
-module DLNC (...);
-input D, G, CLEAR;
-output Q;
-parameter INIT = 1'b0;
-endmodule
-
-
-module DLNCE (...);
-input D, G, CLEAR, CE;
-output Q;
-parameter INIT = 1'b0;
-endmodule
-
-
-module DLNP (...);
-input D, G, PRESET;
-output Q;
-parameter INIT = 1'b1;
-endmodule
-
-
-module DLNPE (...);
-input D, G, PRESET, CE;
-output Q;
-parameter INIT = 1'b1;
-endmodule
-
-
 module INV (...);
 input  I;
 output O;
@@ -421,322 +290,6 @@ output [35:0] DO;
 endmodule
 
 
-module rSDP (...);
-parameter READ_MODE = 1'b0; 
-parameter BIT_WIDTH_0 = 32; 
-parameter BIT_WIDTH_1 = 32; 
-parameter BLK_SEL = 3'b000;
-parameter RESET_MODE = "SYNC"; 
-parameter INIT_RAM_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-input CLKA, CEA, CLKB, CEB;
-input OCE; 
-input RESETA, RESETB; 
-input [13:0] ADA, ADB;
-input [31:0] DI;
-input [2:0] BLKSEL;
-output [31:0] DO;
-endmodule
-
-
-module rSDPX9 (...);
-parameter READ_MODE = 1'b0; 
-parameter BIT_WIDTH_0 = 36; 
-parameter BIT_WIDTH_1 = 36; 
-parameter BLK_SEL = 3'b000;
-parameter RESET_MODE = "SYNC"; 
-parameter INIT_RAM_00 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; 
-parameter INIT_RAM_01 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_02 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_03 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_04 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_05 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_06 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_07 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_08 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_09 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_0A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_0B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_0C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_0D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_0E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_0F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_10 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_11 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_12 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_13 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_14 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_15 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_16 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_17 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_18 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_19 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_1A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_1B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_1C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_1D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_1E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_1F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_20 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_21 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_22 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_23 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_24 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_25 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_26 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_27 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_28 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_29 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_2A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_2B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_2C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_2D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_2E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_2F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_30 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_31 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_32 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_33 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_34 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_35 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_36 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_37 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_38 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_39 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_3A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_3B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_3C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_3D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_3E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_3F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-input CLKA, CEA, CLKB, CEB;
-input OCE; 
-input RESETA, RESETB; 
-input [13:0] ADA, ADB;
-input [2:0] BLKSEL;
-input [35:0] DI;
-output [35:0] DO;
-endmodule
-
-
-module rROM (...);
-parameter READ_MODE = 1'b0; 
-parameter BIT_WIDTH = 32; 
-parameter BLK_SEL = 3'b000;
-parameter RESET_MODE = "SYNC"; 
-parameter INIT_RAM_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-input CLK, CE;
-input OCE; 
-input RESET; 
-input [13:0] AD;
-input [2:0] BLKSEL;
-output [31:0] DO;
-endmodule
-
-
-module rROMX9 (...);
-parameter READ_MODE = 1'b0; 
-parameter BIT_WIDTH = 36; 
-parameter BLK_SEL = 3'b000;
-parameter RESET_MODE = "SYNC"; 
-parameter INIT_RAM_00 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; 
-parameter INIT_RAM_01 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_02 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_03 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_04 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_05 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_06 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_07 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_08 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_09 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_0A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_0B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_0C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_0D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_0E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_0F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_10 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_11 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_12 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_13 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_14 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_15 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_16 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_17 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_18 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_19 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_1A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_1B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_1C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_1D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_1E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_1F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_20 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_21 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_22 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_23 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_24 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_25 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_26 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_27 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_28 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_29 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_2A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_2B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_2C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_2D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_2E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_2F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_30 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_31 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_32 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_33 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_34 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_35 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_36 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_37 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_38 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_39 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_3A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_3B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_3C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_3D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_3E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-parameter INIT_RAM_3F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
-input CLK, CE;
-input OCE; 
-input RESET; 
-input [13:0] AD;
-input [2:0] BLKSEL;
-output [35:0] DO;
-endmodule
-
-
 module pROM (...);
 parameter READ_MODE = 1'b0; 
 parameter BIT_WIDTH = 32; 
@@ -1505,19 +1058,6 @@ inout IO, IOB;
 input I, OEN;
 endmodule
 
-module DLL (...);
-input CLKIN;
-input STOP;
-input UPDNCNTL;
-input RESET;
-output [7:0]STEP;
-output LOCK;
-parameter DLL_FORCE = 0;
-parameter CODESCAL="000";
-parameter SCAL_EN="true";
-parameter DIV_SEL = 1'b0; 
-endmodule
-
 module CLKDIV (...);
 input HCLKIN;
 input RESETN;
@@ -1567,16 +1107,6 @@ input HCLKIN, RESETN;
 output CLKOUT;
 endmodule
 
-module IODELAYA (...);
-parameter C_STATIC_DLY = 0; 
-input DI;
-input  SDTAP;
-input  SETN;
-input  VALUE;
-output DF;
-output DO;
-endmodule
-
 module IBUF_R (...);
 input  I;
 input RTEN;
@@ -1613,97 +1143,6 @@ input [23:0] SPIAD;
 input LOADN_SPIAD;
 endmodule
 
-module CLKDIVG (...);
-input CLKIN;
-input RESETN;
-input CALIB;
-output CLKOUT;
-parameter DIV_MODE = "2"; 
-parameter GSREN = "false"; 
-endmodule
-
-module PLLO (...);
-input CLKIN;
-input CLKFB;
-input RESET;
-input RESET_P;
-input RESET_I;
-input RESET_S;
-input [5:0] FBDSEL;
-input [5:0] IDSEL;
-input [6:0] ODSELA;
-input [6:0] ODSELB;
-input [6:0] ODSELC;
-input [6:0] ODSELD;
-input [3:0] DTA;
-input [3:0] DTB;
-input [4:0] ICPSEL;
-input [2:0] LPFRES;
-input [1:0] PSSEL;
-input PSDIR;
-input PSPULSE;
-input ENCLKA;
-input ENCLKB;
-input ENCLKC;
-input ENCLKD;
-output LOCK;
-output CLKOUTA;
-output CLKOUTB;
-output CLKOUTC;
-output CLKOUTD;
-parameter FCLKIN = "100.0"; 
-parameter DYN_IDIV_SEL= "FALSE";
-parameter IDIV_SEL = 0; 
-parameter DYN_FBDIV_SEL= "FALSE";
-parameter FBDIV_SEL = 0; 
-parameter DYN_ODIVA_SEL= "FALSE";
-parameter ODIVA_SEL = 6; 
-parameter DYN_ODIVB_SEL= "FALSE";
-parameter ODIVB_SEL = 6; 
-parameter DYN_ODIVC_SEL= "FALSE";
-parameter ODIVC_SEL = 6; 
-parameter DYN_ODIVD_SEL= "FALSE";
-parameter ODIVD_SEL = 6; 
-parameter CLKOUTA_EN = "TRUE";
-parameter CLKOUTB_EN = "TRUE";
-parameter CLKOUTC_EN = "TRUE";
-parameter CLKOUTD_EN = "TRUE";
-parameter DYN_DTA_SEL = "FALSE"; 
-parameter DYN_DTB_SEL = "FALSE"; 
-parameter CLKOUTA_DT_DIR = 1'b1; 
-parameter CLKOUTB_DT_DIR = 1'b1; 
-parameter CLKOUTA_DT_STEP = 0; 
-parameter CLKOUTB_DT_STEP = 0; 
-parameter CLKA_IN_SEL = 2'b00;
-parameter CLKA_OUT_SEL = 1'b0;
-parameter CLKB_IN_SEL = 2'b00;
-parameter CLKB_OUT_SEL = 1'b0;
-parameter CLKC_IN_SEL = 2'b00;
-parameter CLKC_OUT_SEL = 1'b0;
-parameter CLKD_IN_SEL = 2'b00;
-parameter CLKD_OUT_SEL = 1'b0;
-parameter CLKFB_SEL = "INTERNAL"; 
-parameter DYN_DPA_EN = "FALSE";
-parameter DYN_PSB_SEL = "FALSE";
-parameter DYN_PSC_SEL = "FALSE";
-parameter DYN_PSD_SEL = "FALSE";
-parameter PSB_COARSE = 1;
-parameter PSB_FINE = 0;
-parameter PSC_COARSE = 1;
-parameter PSC_FINE = 0;
-parameter PSD_COARSE = 1;
-parameter PSD_FINE = 0;
-parameter DTMS_ENB = "FALSE";
-parameter DTMS_ENC = "FALSE";
-parameter DTMS_END = "FALSE";
-parameter RESET_I_EN = "FALSE";
-parameter RESET_S_EN =  "FALSE";
-parameter DYN_ICP_SEL= "FALSE";
-parameter ICP_SEL = 5'bXXXXX;
-parameter DYN_RES_SEL= "FALSE";
-parameter LPR_REF = 7'bXXXXXXX;
-endmodule
-
 module ELVDS_IBUF_MIPI (...);
 output OH, OL;
 input  I, IB;

techlibs/gowin/cells_xtra_gw5a.v

@@ -1,53 +1,6 @@
 // Created by cells_xtra.py
 
 
-module MUX2_MUX8 (...);
-input I0,I1;
-input S0;
-output O;
-endmodule
-
-
-module MUX2_MUX16 (...);
-input I0,I1;
-input S0;
-output O;
-endmodule
-
-
-module MUX2_MUX32 (...);
-input I0,I1;
-input S0;
-output O;
-endmodule
-
-
-module MUX4 (...);
-input I0, I1, I2, I3;
-input S0, S1;
-output O;
-endmodule
-
-
-module MUX8 (...);
-input I0, I1, I2, I3, I4, I5, I6, I7;
-input S0, S1, S2;
-output O;
-endmodule
-
-
-module MUX16 (...);
-input I0, I1, I2, I3, I4, I5, I6, I7, I8, I9, I10, I11, I12, I13, I14, I15;
-input S0, S1, S2, S3;
-output O;
-endmodule
-
-module MUX32 (...);
-input I0, I1, I2, I3, I4, I5, I6, I7, I8, I9, I10, I11, I12, I13, I14, I15, I16, I17, I18, I19, I20, I21, I22, I23, I24, I25, I26, I27, I28, I29, I30, I31;
-input S0, S1, S2, S3, S4;
-output O;
-endmodule
-
 module LUT5 (...);
 parameter INIT = 32'h00000000;
 input I0, I1, I2, I3, I4;
@@ -76,20 +29,6 @@ output F;
 endmodule
 
 
-module DLCE (...);
-input D, G, CLEAR, GE;
-output Q;
-parameter INIT = 1'b0;
-endmodule
-
-
-module DLPE (...);
-input D, G, PRESET, GE;
-output Q;
-parameter INIT = 1'b1;
-endmodule
-
-
 module ROM16 (...);
 parameter INIT_0 = 16'h0000;
 input [3:0] AD;
@@ -141,8 +80,19 @@ endmodule
 module MIPI_OBUF_A (...);
 output O, OB;
 input  I, IB, IL, MODESEL;
-inout IO, IOB;
-input OEN, OENB;
+endmodule
+
+module IBUF_R (...);
+input  I;
+input RTEN;
+output O;
+endmodule
+
+module IOBUF_R (...);
+input I,OEN;
+input RTEN;
+output O;
+inout IO;
 endmodule
 
 module ELVDS_IOBUF_R (...);
@@ -163,21 +113,6 @@ input I, IB;
 input ADCEN;
 endmodule
 
-module MIPI_CPHY_IBUF (...);
-output OH0, OL0, OB0, OH1, OL1, OB1, OH2, OL2, OB2;
-inout IO0, IOB0, IO1, IOB1, IO2, IOB2;
-input  I0, IB0, I1, IB1, I2, IB2;
-input OEN, OENB;
-input HSEN;
-endmodule
-
-module MIPI_CPHY_OBUF (...);
-output O0, OB0, O1, OB1, O2, OB2;
-input  I0, IB0, IL0, I1, IB1, IL1, I2, IB2, IL2;
-inout IO0, IOB0, IO1, IOB1, IO2, IOB2;
-input OEN, OENB, MODESEL, VCOME;
-endmodule
-
 module SDPB (...);
 parameter READ_MODE = 1'b0; 
 parameter BIT_WIDTH_0 = 32; 
@@ -663,8 +598,8 @@ endmodule
 
 
 module SDP36KE (...);
-parameter ECC_WRITE_EN="TRUE"; 
-parameter ECC_READ_EN="TRUE"; 
+parameter ECC_WRITE_EN="FALSE"; 
+parameter ECC_READ_EN="FALSE"; 
 parameter READ_MODE = 1'b0; 
 parameter BLK_SEL_A = 3'b000;
 parameter BLK_SEL_B = 3'b000;
@@ -829,14 +764,6 @@ output [7:0] ECCP;
 endmodule
 
 
-module SDP136K (...);
-input CLKA, CLKB;
-input WE, RE;
-input [10:0] ADA, ADB;
-input [67:0] DI;
-output [67:0] DO;
-endmodule
-
 module MULTADDALU12X12 (...);
 parameter A0REG_CLK = "BYPASS"; 
 parameter A0REG_CE = "CE0"; 
@@ -1053,24 +980,6 @@ input  PSEL;
 input  PADDSUB;
 endmodule
 
-module MULTACC (...);
-output  [23:0] DATAO, CASO;
-input CE, CLK;
-input [5:0] COFFIN0, COFFIN1, COFFIN2;
-input [9:0] DATAIN0, DATAIN1;
-input [9:0] DATAIN2;
-input RSTN;
-input [23:0] CASI;
-parameter COFFIN_WIDTH = 4; 
-parameter DATAIN_WIDTH = 8; 
-parameter IREG = 1'b0; 
-parameter OREG = 1'b0; 
-parameter PREG = 1'b0; 
-parameter ACC_EN = "FALSE";  
-parameter CASI_EN = "FALSE"; 
-parameter CASO_EN = "FALSE"; 
-endmodule
-
 module IDDR_MEM (...);
 input D, ICLK, PCLK;
 input [2:0] WADDR;
@@ -1157,39 +1066,13 @@ output [31:0] Q;
 input D;
 input PCLK, FCLKP, FCLKN, FCLKQP, FCLKQN;
 input RESET;
-output DF0, DF1;
-input  SDTAP0, SDTAP1;
-input  VALUE0,VALUE1;
-input  [7:0] DLYSTEP0,DLYSTEP1;
-parameter C_STATIC_DLY_0 = 0; 
-parameter DYN_DLY_EN_0 = "FALSE";
-parameter ADAPT_EN_0 = "FALSE";
-parameter C_STATIC_DLY_1 = 0; 
-parameter DYN_DLY_EN_1 = "FALSE";
-parameter ADAPT_EN_1 = "FALSE";
-endmodule
-
-module OSIDES64 (...);
-output [63:0] Q;
-input D;
-input PCLK, FCLKP, FCLKN, FCLKQP, FCLKQN;
-input RESET;
-output DF0, DF1, DF2, DF3;
-input  SDTAP0, SDTAP1, SDTAP2, SDTAP3;
-input  VALUE0, VALUE1, VALUE2, VALUE3;
-input  [7:0] DLYSTEP0, DLYSTEP1, DLYSTEP2, DLYSTEP3;
-parameter C_STATIC_DLY_0 = 0; 
-parameter DYN_DLY_EN_0 = "FALSE";
-parameter ADAPT_EN_0 = "FALSE";
-parameter C_STATIC_DLY_1 = 0; 
-parameter DYN_DLY_EN_1 = "FALSE";
-parameter ADAPT_EN_1 = "FALSE";
-parameter C_STATIC_DLY_2 = 0; 
-parameter DYN_DLY_EN_2 = "FALSE";
-parameter ADAPT_EN_2 = "FALSE";
-parameter C_STATIC_DLY_3 = 0; 
-parameter DYN_DLY_EN_3 = "FALSE";
-parameter ADAPT_EN_3 = "FALSE";
+output DF;
+input  SDTAP;
+input  VALUE;
+input  [7:0] DLYSTEP;
+parameter C_STATIC_DLY = 0; 
+parameter DYN_DLY_EN = "FALSE";
+parameter ADAPT_EN = "FALSE";
 endmodule
 
 module DCE (...);
@@ -1249,17 +1132,6 @@ output OSCOUT;
 input OSCEN;
 endmodule
 
-module OSCB (...);
-parameter FREQ_MODE = "25"; 
-parameter FREQ_DIV = 10; 
-parameter DYN_TRIM_EN = "FALSE"; 
-output OSCOUT;
-output OSCREF;
-input OSCEN, FMODE;
-input [7:0] RTRIM;
-input [5:0] RTCTRIM; 
-endmodule
-
 module PLL (...);
 input CLKIN;
 input CLKFB;
@@ -1699,8 +1571,8 @@ input ADWSEL;
 endmodule
 
 module OTP (...);
-parameter MODE = 2'b01; 
-input CLK, READ, SHIFT;
+parameter MODE = 1'b0; 
+input READ, SHIFT;
 output DOUT;
 endmodule
 
@@ -1743,31 +1615,6 @@ input ERR0INJECT,ERR1INJECT;
 input [6:0] ERRINJ0LOC,ERRINJ1LOC;
 endmodule
 
-module CMSERB (...);
-output RUNNING;
-output CRCERR;
-output CRCDONE;
-output ECCCORR;
-output ECCUNCORR; 
-output [12:0] ERRLOC;
-output ECCDEC;
-output DSRRD;
-output DSRWR; 
-output ASRRESET;
-output ASRINC;
-output REFCLK;
-input CLK;
-input [2:0] SEREN;
-input ERR0INJECT,ERR1INJECT;
-input [6:0] ERRINJ0LOC,ERRINJ1LOC;
-endmodule
-
-module SAMBA (...);
-parameter MODE = 2'b00; 
-input SPIAD;
-input LOAD;
-endmodule
-
 module ADCLRC (...);
 endmodule
 
@@ -1777,150 +1624,6 @@ endmodule
 module ADC (...);
 endmodule
 
-module MIPI_DPHY_RX (...);
-output D0LN_DESKEW_DONE,D1LN_DESKEW_DONE,D2LN_DESKEW_DONE,D3LN_DESKEW_DONE;
-output [15:0] D0LN_HSRXD, D1LN_HSRXD, D2LN_HSRXD, D3LN_HSRXD;
-output D0LN_HSRXD_VLD,D1LN_HSRXD_VLD,D2LN_HSRXD_VLD,D3LN_HSRXD_VLD;
-output DI_LPRX0_N, DI_LPRX0_P, DI_LPRX1_N, DI_LPRX1_P, DI_LPRX2_N, DI_LPRX2_P, DI_LPRX3_N, DI_LPRX3_P;
-output DI_LPRXCK_N, DI_LPRXCK_P;
-output RX_CLK_O;          
-output DESKEW_ERROR;      
-inout  CK_N, CK_P, RX0_N, RX0_P, RX1_N, RX1_P, RX2_N, RX2_P, RX3_N, RX3_P;
-input BYTE_LENDIAN;       
-input [2:0] FIFO_RD_STD;  
-input HSRX_STOP;          
-input PWRON;              
-input RESET;              
-input D0LN_HSRX_DREN,  D1LN_HSRX_DREN, D2LN_HSRX_DREN, D3LN_HSRX_DREN;
-input DESKEW_BY,DESKEW_EN_OEDGE;
-input [5:0] DESKEW_HALF_OPENING;
-input [2:0] DESKEW_LNSEL; 
-input [1:0] DESKEW_LSB_MODE;
-input [2:0] DESKEW_M;
-input [12:0] DESKEW_MTH;   
-input [6:0] DESKEW_MSET;
-input DESKEW_OCLKEDG_EN;
-input [6:0] DESKEW_OWVAL;
-input DESKEW_REQ;         
-input DO_LPTX0_N, DO_LPTX0_P, DO_LPTX1_N, DO_LPTX1_P, DO_LPTX2_N, DO_LPTX2_P, DO_LPTX3_N, DO_LPTX3_P;
-input DO_LPTXCK_N, DO_LPTXCK_P;
-input DRST_N;             
-input [2:0] EQCS_LANE0,EQCS_LANE1,EQCS_LANE2,EQCS_LANE3,EQCS_CK;
-input [2:0] EQRS_LANE0,EQRS_LANE1,EQRS_LANE2,EQRS_LANE3,EQRS_CK;
-input HS_8BIT_MODE;       
-input HSRX_DLYDIR_LANE0, HSRX_DLYDIR_LANE1,HSRX_DLYDIR_LANE2,HSRX_DLYDIR_LANE3,HSRX_DLYDIR_CK;
-input HSRX_DLYLDN_LANE0, HSRX_DLYLDN_LANE1,HSRX_DLYLDN_LANE2,HSRX_DLYLDN_LANE3,HSRX_DLYLDN_CK;
-input HSRX_DLYMV_LANE0, HSRX_DLYMV_LANE1,HSRX_DLYMV_LANE2,HSRX_DLYMV_LANE3,HSRX_DLYMV_CK;
-input HSRX_EN_CK;         
-input HSRX_ODTEN_CK, HSRX_ODTEN_D0,  HSRX_ODTEN_D1, HSRX_ODTEN_D2, HSRX_ODTEN_D3;
-input LALIGN_EN;          
-input LPRX_EN_CK, LPRX_EN_D0, LPRX_EN_D1, LPRX_EN_D2, LPRX_EN_D3;
-input LPTX_EN_CK, LPTX_EN_D0, LPTX_EN_D1, LPTX_EN_D2, LPTX_EN_D3;
-input ONE_BYTE0_MATCH;    
-input RX_CLK_1X;          
-input RX_INVERT;          
-input WALIGN_BY;          
-input WALIGN_DVLD;
-input WORD_LENDIAN;       
-parameter ALIGN_BYTE = 8'b10111000;
-parameter EN_CLKB1X = 1'b1;
-parameter EQ_ADPSEL_LANE0 = 1'b0;
-parameter EQ_ADPSEL_LANE1 = 1'b0;
-parameter EQ_ADPSEL_LANE2 = 1'b0;
-parameter EQ_ADPSEL_LANE3 = 1'b0;
-parameter EQ_ADPSEL_CK = 1'b0;
-parameter EQ_CS_LANE0 = 3'b100;
-parameter EQ_CS_LANE1 = 3'b100;
-parameter EQ_CS_LANE2 = 3'b100;
-parameter EQ_CS_LANE3 = 3'b100;
-parameter EQ_CS_CK = 3'b100;
-parameter EQ_PBIAS_LANE0 = 4'b0100;
-parameter EQ_PBIAS_LANE1 = 4'b0100;
-parameter EQ_PBIAS_LANE2 = 4'b0100;
-parameter EQ_PBIAS_LANE3 = 4'b0100;
-parameter EQ_PBIAS_CK = 4'b0100;
-parameter EQ_RS_LANE0 = 3'b100;
-parameter EQ_RS_LANE1 = 3'b100;
-parameter EQ_RS_LANE2 = 3'b100;
-parameter EQ_RS_LANE3 = 3'b100;
-parameter EQ_RS_CK = 3'b100;
-parameter EQ_ZLD_LANE0 = 4'b1000;
-parameter EQ_ZLD_LANE1 = 4'b1000;
-parameter EQ_ZLD_LANE2 = 4'b1000;
-parameter EQ_ZLD_LANE3 = 4'b1000;
-parameter EQ_ZLD_CK = 4'b1000;
-parameter HIGH_BW_LANE0 = 1'b1;
-parameter HIGH_BW_LANE1 = 1'b1;
-parameter HIGH_BW_LANE2 = 1'b1;
-parameter HIGH_BW_LANE3 = 1'b1;
-parameter HIGH_BW_CK = 1'b1;
-parameter HSRX_DLYCTL_CK = 7'b0000000;
-parameter HSRX_DLYCTL_LANE0 = 7'b0000000;
-parameter HSRX_DLYCTL_LANE1 = 7'b0000000;
-parameter HSRX_DLYCTL_LANE2 = 7'b0000000;
-parameter HSRX_DLYCTL_LANE3 = 7'b0000000;
-parameter HSRX_DLY_SEL = 1'b0;
-parameter HSRX_DUTY_LANE0 = 4'b1000;
-parameter HSRX_DUTY_LANE1 = 4'b1000;
-parameter HSRX_DUTY_LANE2 = 4'b1000;
-parameter HSRX_DUTY_LANE3 = 4'b1000;
-parameter HSRX_DUTY_CK = 4'b1000;
-parameter HSRX_EN = 1'b1;
-parameter HSRX_EQ_EN_LANE0 = 1'b1;
-parameter HSRX_EQ_EN_LANE1 = 1'b1;
-parameter HSRX_EQ_EN_LANE2 = 1'b1;
-parameter HSRX_EQ_EN_LANE3 = 1'b1;
-parameter HSRX_EQ_EN_CK = 1'b1;
-parameter HSRX_IBIAS = 4'b0011;
-parameter HSRX_IMARG_EN = 1'b1;
-parameter MIPI_LANE0_EN = 1'b0;
-parameter MIPI_LANE1_EN = 1'b0;
-parameter MIPI_LANE2_EN = 1'b0;
-parameter MIPI_LANE3_EN = 1'b0;
-parameter MIPI_CK_EN = 1'b1;
-parameter HSRX_ODT_EN = 1'b1;
-parameter HSRX_ODT_TST = 4'b0000;
-parameter HSRX_ODT_TST_CK = 1'b0;
-parameter HSRX_STOP_EN = 1'b0;
-parameter HSRX_TST = 4'b0000;
-parameter HSRX_TST_CK = 1'b0;
-parameter HSRX_WAIT4EDGE = 1'b0;
-parameter HYST_NCTL = 2'b01;
-parameter HYST_PCTL = 2'b01;
-parameter LOW_LPRX_VTH = 1'b0;
-parameter LPRX_EN = 1'b1;
-parameter LPRX_TST = 4'b0000;
-parameter LPRX_TST_CK = 1'b0;
-parameter LPTX_EN = 1'b1;
-parameter LPTX_SW_LANE0 = 3'b100;
-parameter LPTX_SW_LANE1 = 3'b100;
-parameter LPTX_SW_LANE2 = 3'b100;
-parameter LPTX_SW_LANE3 = 3'b100;
-parameter LPTX_SW_CK = 3'b100;
-parameter LPTX_TST = 4'b0000;
-parameter LPTX_TST_CK = 1'b0;
-parameter MIPI_DIS_N = 1'b1;
-parameter PGA_BIAS_LANE0 =  4'b1000;
-parameter PGA_BIAS_LANE1 =  4'b1000;
-parameter PGA_BIAS_LANE2 =  4'b1000;
-parameter PGA_BIAS_LANE3 =  4'b1000;
-parameter PGA_BIAS_CK =  4'b1000;
-parameter PGA_GAIN_LANE0 =  4'b1000;
-parameter PGA_GAIN_LANE1 =  4'b1000;
-parameter PGA_GAIN_LANE2 =  4'b1000;
-parameter PGA_GAIN_LANE3 =  4'b1000;
-parameter PGA_GAIN_CK =  4'b1000;
-parameter RX_CLK1X_SYNC_SEL = 1'b0;
-parameter RX_ODT_TRIM_LANE0 = 4'b0111;
-parameter RX_ODT_TRIM_LANE1 = 4'b0111;
-parameter RX_ODT_TRIM_LANE2 = 4'b0111;
-parameter RX_ODT_TRIM_LANE3 = 4'b0111;
-parameter RX_ODT_TRIM_CK = 4'b0111;
-parameter STP_UNIT = 2'b00;
-parameter SYNC_CLK_SEL = 1'b1;
-parameter WALIGN_DVLD_SRC_SEL = 1'b0;
-endmodule
-
 module MIPI_DPHY (...);
 output RX_CLK_O, TX_CLK_O;
 output [15:0] D0LN_HSRXD, D1LN_HSRXD, D2LN_HSRXD, D3LN_HSRXD;
@@ -1928,14 +1631,14 @@ output D0LN_HSRXD_VLD,D1LN_HSRXD_VLD,D2LN_HSRXD_VLD,D3LN_HSRXD_VLD;
 input  D0LN_HSRX_DREN, D1LN_HSRX_DREN,  D2LN_HSRX_DREN,  D3LN_HSRX_DREN;
 output  DI_LPRX0_N, DI_LPRX0_P, DI_LPRX1_N, DI_LPRX1_P, DI_LPRX2_N,  DI_LPRX2_P, DI_LPRX3_N, DI_LPRX3_P, DI_LPRXCK_N, DI_LPRXCK_P;
 inout  CK_N, CK_P, D0_N, D0_P, D1_N, D1_P, D2_N, D2_P, D3_N, D3_P;
-input HSRX_STOP, HSTXEN_LN0, HSTXEN_LN1, HSTXEN_LN2, HSTXEN_LN3, HSTXEN_LNCK;
+input HSRX_STOP, HSTXEN_LN0, HSTXEN_LN1, HSTXEN_LN2, HSTXEN_LN3, HSTXEN_LNCK,
 input PWRON_RX, PWRON_TX, RESET, RX_CLK_1X, TX_CLK_1X;
 input TXDPEN_LN0, TXDPEN_LN1, TXDPEN_LN2, TXDPEN_LN3, TXDPEN_LNCK, TXHCLK_EN;
 input [15:0]  CKLN_HSTXD,D0LN_HSTXD,D1LN_HSTXD,D2LN_HSTXD,D3LN_HSTXD;
 input HSTXD_VLD;
 input CK0, CK90, CK180, CK270;
 input DO_LPTX0_N, DO_LPTX1_N, DO_LPTX2_N, DO_LPTX3_N, DO_LPTXCK_N, DO_LPTX0_P, DO_LPTX1_P, DO_LPTX2_P, DO_LPTX3_P, DO_LPTXCK_P;
-input HSRX_EN_CK, HSRX_EN_D0, HSRX_EN_D1, HSRX_EN_D2, HSRX_EN_D3, HSRX_ODTEN_CK;
+input HSRX_EN_CK, HSRX_EN_D0, HSRX_EN_D1, HSRX_EN_D2, HSRX_EN_D3, HSRX_ODTEN_CK, 
 input RX_DRST_N, TX_DRST_N, WALIGN_DVLD;
 output [7:0] MRDATA;
 input MA_INC, MCLK;
@@ -2011,7 +1714,7 @@ parameter        RX_RD_START_DEPTH              = 5'b00001;
 parameter        RX_SYNC_MODE                   = 1'b0 ; 
 parameter        RX_WORD_ALIGN_BYPASS           = 1'b0 ; 
 parameter        RX_WORD_ALIGN_DATA_VLD_SRC_SEL = 1'b0 ; 
-parameter        RX_WORD_LITTLE_ENDIAN          = 1'b1 ; 
+parameter        RX_WORD_LITTLE_ENDIAN          = 1'b0 ; 
 parameter        TX_BYPASS_MODE                 = 1'b0 ; 
 parameter        TX_BYTECLK_SYNC_MODE           = 1'b0 ; 
 parameter        TX_OCLK_USE_CIBCLK             = 1'b0 ; 
@@ -2214,434 +1917,6 @@ parameter        TEST_P_IMP_LN3                 = 1'b0 ;
 parameter        TEST_P_IMP_LNCK                = 1'b0 ;   
 endmodule
 
-module MIPI_DPHYA (...);
-output RX_CLK_O, TX_CLK_O;
-output [15:0] D0LN_HSRXD, D1LN_HSRXD, D2LN_HSRXD, D3LN_HSRXD;
-output D0LN_HSRXD_VLD,D1LN_HSRXD_VLD,D2LN_HSRXD_VLD,D3LN_HSRXD_VLD;
-input  D0LN_HSRX_DREN, D1LN_HSRX_DREN,  D2LN_HSRX_DREN,  D3LN_HSRX_DREN;
-output  DI_LPRX0_N, DI_LPRX0_P, DI_LPRX1_N, DI_LPRX1_P, DI_LPRX2_N,  DI_LPRX2_P, DI_LPRX3_N, DI_LPRX3_P, DI_LPRXCK_N, DI_LPRXCK_P;
-inout  CK_N, CK_P, D0_N, D0_P, D1_N, D1_P, D2_N, D2_P, D3_N, D3_P;
-input HSRX_STOP, HSTXEN_LN0, HSTXEN_LN1, HSTXEN_LN2, HSTXEN_LN3, HSTXEN_LNCK;
-input PWRON_RX, PWRON_TX, RESET, RX_CLK_1X, TX_CLK_1X;
-input TXDPEN_LN0, TXDPEN_LN1, TXDPEN_LN2, TXDPEN_LN3, TXDPEN_LNCK, TXHCLK_EN;
-input [15:0]  CKLN_HSTXD,D0LN_HSTXD,D1LN_HSTXD,D2LN_HSTXD,D3LN_HSTXD;
-input HSTXD_VLD;
-input CK0, CK90, CK180, CK270;
-input DO_LPTX0_N, DO_LPTX1_N, DO_LPTX2_N, DO_LPTX3_N, DO_LPTXCK_N, DO_LPTX0_P, DO_LPTX1_P, DO_LPTX2_P, DO_LPTX3_P, DO_LPTXCK_P;
-input HSRX_EN_CK, HSRX_EN_D0, HSRX_EN_D1, HSRX_EN_D2, HSRX_EN_D3, HSRX_ODTEN_CK;
-input RX_DRST_N, TX_DRST_N, WALIGN_DVLD;
-output [7:0] MRDATA;
-input MA_INC, MCLK;
-input [1:0] MOPCODE;
-input [7:0] MWDATA;
-input SPLL_CKN, SPLL_CKP;
-output  ALPEDO_LANE0, ALPEDO_LANE1, ALPEDO_LANE2, ALPEDO_LANE3, ALPEDO_LANECK;
-output D1LN_DESKEW_DONE,D2LN_DESKEW_DONE,D3LN_DESKEW_DONE,D0LN_DESKEW_DONE;
-output D1LN_DESKEW_ERROR, D2LN_DESKEW_ERROR, D3LN_DESKEW_ERROR, D0LN_DESKEW_ERROR;
-input D0LN_DESKEW_REQ, D1LN_DESKEW_REQ, D2LN_DESKEW_REQ, D3LN_DESKEW_REQ;
-input HSRX_DLYDIR_LANE0, HSRX_DLYDIR_LANE1, HSRX_DLYDIR_LANE2, HSRX_DLYDIR_LANE3, HSRX_DLYDIR_LANECK;
-input HSRX_DLYLDN_LANE0, HSRX_DLYLDN_LANE1, HSRX_DLYLDN_LANE2, HSRX_DLYLDN_LANE3, HSRX_DLYLDN_LANECK;
-input HSRX_DLYMV_LANE0, HSRX_DLYMV_LANE1,  HSRX_DLYMV_LANE2, HSRX_DLYMV_LANE3, HSRX_DLYMV_LANECK;
-input  ALP_EDEN_LANE0, ALP_EDEN_LANE1, ALP_EDEN_LANE2, ALP_EDEN_LANE3, ALP_EDEN_LANECK, ALPEN_LN0, ALPEN_LN1, ALPEN_LN2, ALPEN_LN3, ALPEN_LNCK;
-parameter        TX_PLLCLK = "NONE"; 
-parameter        RX_ALIGN_BYTE                  = 8'b10111000 ; 
-parameter        RX_HS_8BIT_MODE                = 1'b0 ; 
-parameter        RX_LANE_ALIGN_EN               = 1'b0 ; 
-parameter        TX_HS_8BIT_MODE                = 1'b0 ; 
-parameter        HSREG_EN_LN0                   = 1'b0;  
-parameter        HSREG_EN_LN1                   = 1'b0;  
-parameter        HSREG_EN_LN2                   = 1'b0;  
-parameter        HSREG_EN_LN3                   = 1'b0;  
-parameter        HSREG_EN_LNCK                  = 1'b0;  
-parameter        LANE_DIV_SEL                   = 2'b00;  
-parameter        HSRX_EN                        = 1'b1 ;  
-parameter        HSRX_LANESEL                   = 4'b1111 ;   
-parameter        HSRX_LANESEL_CK                = 1'b1 ;   
-parameter        HSTX_EN_LN0                    = 1'b0 ;   
-parameter        HSTX_EN_LN1                    = 1'b0 ;   
-parameter        HSTX_EN_LN2                    = 1'b0 ;   
-parameter        HSTX_EN_LN3                    = 1'b0 ;   
-parameter        HSTX_EN_LNCK                   = 1'b0 ;   
-parameter        LPTX_EN_LN0                    = 1'b1 ;   
-parameter        LPTX_EN_LN1                    = 1'b1 ;   
-parameter        LPTX_EN_LN2                    = 1'b1 ;   
-parameter        LPTX_EN_LN3                    = 1'b1 ;   
-parameter        LPTX_EN_LNCK                   = 1'b1 ;   
-parameter        TXDP_EN_LN0                    = 1'b0 ;  
-parameter        TXDP_EN_LN1                    = 1'b0 ;   
-parameter        TXDP_EN_LN2                    = 1'b0 ;   
-parameter        TXDP_EN_LN3                    = 1'b0 ;   
-parameter        TXDP_EN_LNCK                   = 1'b0 ;
-parameter        SPLL_DIV_SEL                   = 2'b00;
-parameter        DPHY_CK_SEL                    = 2'b01;
-parameter        CKLN_DELAY_EN                  = 1'b0;  
-parameter        CKLN_DELAY_OVR_VAL             = 7'b0000000; 
-parameter        D0LN_DELAY_EN                  = 1'b0;  
-parameter        D0LN_DELAY_OVR_VAL             = 7'b0000000; 
-parameter        D0LN_DESKEW_BYPASS             = 1'b0;  
-parameter        D1LN_DELAY_EN                  = 1'b0;  
-parameter        D1LN_DELAY_OVR_VAL             = 7'b0000000; 
-parameter        D1LN_DESKEW_BYPASS             = 1'b0;  
-parameter        D2LN_DELAY_EN                  = 1'b0;  
-parameter        D2LN_DELAY_OVR_VAL             = 7'b0000000; 
-parameter        D2LN_DESKEW_BYPASS             = 1'b0;  
-parameter        D3LN_DELAY_EN                  = 1'b0;  
-parameter        D3LN_DELAY_OVR_VAL             = 7'b0000000; 
-parameter        D3LN_DESKEW_BYPASS             = 1'b0;  
-parameter        DESKEW_EN_LOW_DELAY            = 1'b0;  
-parameter        DESKEW_EN_ONE_EDGE             = 1'b0;  
-parameter        DESKEW_FAST_LOOP_TIME          = 4'b0000;  
-parameter        DESKEW_FAST_MODE               = 1'b0;  
-parameter        DESKEW_HALF_OPENING            = 6'b010110; 
-parameter        DESKEW_LSB_MODE                = 2'b00;  
-parameter        DESKEW_M                       = 3'b011;  
-parameter        DESKEW_M_TH                    = 13'b0000110100110; 
-parameter        DESKEW_MAX_SETTING           = 7'b0100001; 
-parameter        DESKEW_ONE_CLK_EDGE_EN       = 1'b0 ; 
-parameter        DESKEW_RST_BYPASS              = 1'b0 ; 
-parameter        RX_BYTE_LITTLE_ENDIAN          = 1'b1 ; 
-parameter        RX_CLK_1X_SYNC_SEL             = 1'b0 ; 
-parameter        RX_INVERT                      = 1'b0 ; 
-parameter        RX_ONE_BYTE0_MATCH             = 1'b0 ; 
-parameter        RX_RD_START_DEPTH              = 5'b00001; 
-parameter        RX_SYNC_MODE                   = 1'b0 ; 
-parameter        RX_WORD_ALIGN_BYPASS           = 1'b0 ; 
-parameter        RX_WORD_ALIGN_DATA_VLD_SRC_SEL = 1'b0 ; 
-parameter        RX_WORD_LITTLE_ENDIAN          = 1'b1 ; 
-parameter        TX_BYPASS_MODE                 = 1'b0 ; 
-parameter        TX_BYTECLK_SYNC_MODE           = 1'b0 ; 
-parameter        TX_OCLK_USE_CIBCLK             = 1'b0 ; 
-parameter        TX_RD_START_DEPTH              = 5'b00001; 
-parameter        TX_SYNC_MODE                   = 1'b0 ; 
-parameter        TX_WORD_LITTLE_ENDIAN          = 1'b1 ; 
-parameter        EQ_CS_LANE0                    = 3'b100;  
-parameter        EQ_CS_LANE1                    = 3'b100;  
-parameter        EQ_CS_LANE2                    = 3'b100;  
-parameter        EQ_CS_LANE3                    = 3'b100;  
-parameter        EQ_CS_LANECK                   = 3'b100;  
-parameter        EQ_RS_LANE0                    = 3'b100;  
-parameter        EQ_RS_LANE1                    = 3'b100;  
-parameter        EQ_RS_LANE2                    = 3'b100;  
-parameter        EQ_RS_LANE3                    = 3'b100;  
-parameter        EQ_RS_LANECK                   = 3'b100;  
-parameter        HSCLK_LANE_LN0                 = 1'b0;  
-parameter        HSCLK_LANE_LN1                 = 1'b0;  
-parameter        HSCLK_LANE_LN2                 = 1'b0;  
-parameter        HSCLK_LANE_LN3                 = 1'b0;  
-parameter        HSCLK_LANE_LNCK                = 1'b1;  
-parameter        ALP_ED_EN_LANE0                = 1'b1 ; 
-parameter        ALP_ED_EN_LANE1                = 1'b1 ;  
-parameter        ALP_ED_EN_LANE2                = 1'b1 ;  
-parameter        ALP_ED_EN_LANE3                = 1'b1 ;  
-parameter        ALP_ED_EN_LANECK               = 1'b1 ; 
-parameter        ALP_ED_TST_LANE0               = 1'b0 ;  
-parameter        ALP_ED_TST_LANE1               = 1'b0 ;  
-parameter        ALP_ED_TST_LANE2               = 1'b0 ;  
-parameter        ALP_ED_TST_LANE3               = 1'b0 ;  
-parameter        ALP_ED_TST_LANECK              = 1'b0 ;  
-parameter        ALP_EN_LN0                     = 1'b0 ; 
-parameter        ALP_EN_LN1                     = 1'b0 ;  
-parameter        ALP_EN_LN2                     = 1'b0 ;  
-parameter        ALP_EN_LN3                     = 1'b0 ; 
-parameter        ALP_EN_LNCK                    = 1'b0 ; 
-parameter        ALP_HYS_EN_LANE0               = 1'b1 ;  
-parameter        ALP_HYS_EN_LANE1               = 1'b1 ;  
-parameter        ALP_HYS_EN_LANE2               = 1'b1 ;  
-parameter        ALP_HYS_EN_LANE3               = 1'b1 ;  
-parameter        ALP_HYS_EN_LANECK              = 1'b1 ;  
-parameter        ALP_TH_LANE0                   = 4'b1000 ;   
-parameter        ALP_TH_LANE1                   = 4'b1000 ;   
-parameter        ALP_TH_LANE2                   = 4'b1000 ;   
-parameter        ALP_TH_LANE3                   = 4'b1000 ;   
-parameter        ALP_TH_LANECK                  = 4'b1000 ;   
-parameter        ANA_BYTECLK_PH                 = 2'b00 ;  
-parameter        BIT_REVERSE_LN0                = 1'b0 ;  
-parameter        BIT_REVERSE_LN1                = 1'b0 ;  
-parameter        BIT_REVERSE_LN2                = 1'b0 ;  
-parameter        BIT_REVERSE_LN3                = 1'b0 ;  
-parameter        BIT_REVERSE_LNCK               = 1'b0 ;  
-parameter        BYPASS_TXHCLKEN                = 1'b1 ;  
-parameter        BYPASS_TXHCLKEN_SYNC           = 1'b0 ;  
-parameter        BYTE_CLK_POLAR                 = 1'b0 ;  
-parameter        BYTE_REVERSE_LN0               = 1'b0 ;  
-parameter        BYTE_REVERSE_LN1               = 1'b0 ;  
-parameter        BYTE_REVERSE_LN2               = 1'b0 ;  
-parameter        BYTE_REVERSE_LN3               = 1'b0 ;  
-parameter        BYTE_REVERSE_LNCK              = 1'b0 ;  
-parameter        EN_CLKB1X                      = 1'b1 ;  
-parameter        EQ_PBIAS_LANE0                 = 4'b1000 ;   
-parameter        EQ_PBIAS_LANE1                 = 4'b1000 ;   
-parameter        EQ_PBIAS_LANE2                 = 4'b1000 ;   
-parameter        EQ_PBIAS_LANE3                 = 4'b1000 ;   
-parameter        EQ_PBIAS_LANECK                = 4'b1000 ;   
-parameter        EQ_ZLD_LANE0                   = 4'b1000 ;   
-parameter        EQ_ZLD_LANE1                   = 4'b1000 ;   
-parameter        EQ_ZLD_LANE2                   = 4'b1000 ;   
-parameter        EQ_ZLD_LANE3                   = 4'b1000 ;   
-parameter        EQ_ZLD_LANECK                  = 4'b1000 ;   
-parameter        HIGH_BW_LANE0                  = 1'b1 ;   
-parameter        HIGH_BW_LANE1                  = 1'b1 ;   
-parameter        HIGH_BW_LANE2                  = 1'b1 ;   
-parameter        HIGH_BW_LANE3                  = 1'b1 ;   
-parameter        HIGH_BW_LANECK                 = 1'b1 ;   
-parameter        HSREG_VREF_CTL                 = 3'b100 ;   
-parameter        HSREG_VREF_EN                  = 1'b1 ;  
-parameter        HSRX_DLY_CTL_CK                = 7'b0000000 ;   
-parameter        HSRX_DLY_CTL_LANE0             = 7'b0000000 ;   
-parameter        HSRX_DLY_CTL_LANE1             = 7'b0000000 ;   
-parameter        HSRX_DLY_CTL_LANE2             = 7'b0000000 ;   
-parameter        HSRX_DLY_CTL_LANE3             = 7'b0000000 ;   
-parameter        HSRX_DLY_SEL_LANE0             = 1'b0 ;  
-parameter        HSRX_DLY_SEL_LANE1             = 1'b0 ;   
-parameter        HSRX_DLY_SEL_LANE2             = 1'b0 ;   
-parameter        HSRX_DLY_SEL_LANE3             = 1'b0 ;   
-parameter        HSRX_DLY_SEL_LANECK            = 1'b0 ;   
-parameter        HSRX_DUTY_LANE0                = 4'b1000 ;  
-parameter        HSRX_DUTY_LANE1                = 4'b1000 ;  
-parameter        HSRX_DUTY_LANE2                = 4'b1000 ;  
-parameter        HSRX_DUTY_LANE3                = 4'b1000 ;  
-parameter        HSRX_DUTY_LANECK               = 4'b1000 ;  
-parameter        HSRX_EQ_EN_LANE0               = 1'b1 ;  
-parameter        HSRX_EQ_EN_LANE1               = 1'b1 ;  
-parameter        HSRX_EQ_EN_LANE2               = 1'b1 ;  
-parameter        HSRX_EQ_EN_LANE3               = 1'b1 ;  
-parameter        HSRX_EQ_EN_LANECK              = 1'b1 ;  
-parameter        HSRX_IBIAS                     = 4'b0011 ;   
-parameter        HSRX_IBIAS_TEST_EN             = 1'b0 ;   
-parameter        HSRX_IMARG_EN                  = 1'b0 ;   
-parameter        HSRX_ODT_EN                    = 1'b1 ;   
-parameter        HSRX_ODT_TST                   = 4'b0000 ;   
-parameter        HSRX_ODT_TST_CK                = 1'b0 ;   
-parameter        HSRX_SEL                       = 4'b0000 ;   
-parameter        HSRX_STOP_EN                   = 1'b0 ; 
-parameter        HSRX_TST                       = 4'b0000 ;   
-parameter        HSRX_TST_CK                    = 1'b0 ;   
-parameter        HSRX_WAIT4EDGE                 = 1'b1 ;   
-parameter        HYST_NCTL                      = 2'b01 ;  
-parameter        HYST_PCTL                      = 2'b01 ;  
-parameter        IBIAS_TEST_EN                  = 1'b0 ;   
-parameter        LB_CH_SEL                      = 1'b0 ;   
-parameter        LB_EN_LN0                      = 1'b0 ;   
-parameter        LB_EN_LN1                      = 1'b0 ;   
-parameter        LB_EN_LN2                      = 1'b0 ;   
-parameter        LB_EN_LN3                      = 1'b0 ;   
-parameter        LB_EN_LNCK                     = 1'b0 ;   
-parameter        LB_POLAR_LN0                   = 1'b0 ;   
-parameter        LB_POLAR_LN1                   = 1'b0 ;   
-parameter        LB_POLAR_LN2                   = 1'b0 ;   
-parameter        LB_POLAR_LN3                   = 1'b0 ;   
-parameter        LB_POLAR_LNCK                  = 1'b0 ;   
-parameter        LOW_LPRX_VTH                   = 1'b0 ;   
-parameter        LPBK_DATA2TO1                  = 4'b0000;  
-parameter        LPBK_DATA2TO1_CK               = 1'b0 ;   
-parameter        LPBK_EN                        = 1'b0 ;   
-parameter        LPBK_SEL                       = 4'b0000;  
-parameter        LPBKTST_EN                     = 4'b0000;  
-parameter        LPBKTST_EN_CK                  = 1'b0 ;   
-parameter        LPRX_EN                        = 1'b1 ;   
-parameter        LPRX_TST                       = 4'b0000;  
-parameter        LPRX_TST_CK                    = 1'b0 ;   
-parameter        LPTX_DAT_POLAR_LN0             = 1'b0 ;   
-parameter        LPTX_DAT_POLAR_LN1             = 1'b0 ;   
-parameter        LPTX_DAT_POLAR_LN2             = 1'b0 ;   
-parameter        LPTX_DAT_POLAR_LN3             = 1'b0 ;   
-parameter        LPTX_DAT_POLAR_LNCK            = 1'b0 ;   
-parameter        LPTX_NIMP_LN0                  = 3'b100 ; 
-parameter        LPTX_NIMP_LN1                  = 3'b100 ; 
-parameter        LPTX_NIMP_LN2                  = 3'b100 ; 
-parameter        LPTX_NIMP_LN3                  = 3'b100 ; 
-parameter        LPTX_NIMP_LNCK                 = 3'b100 ; 
-parameter        LPTX_PIMP_LN0                  = 3'b100 ; 
-parameter        LPTX_PIMP_LN1                  = 3'b100 ; 
-parameter        LPTX_PIMP_LN2                  = 3'b100 ; 
-parameter        LPTX_PIMP_LN3                  = 3'b100 ; 
-parameter        LPTX_PIMP_LNCK                 = 3'b100 ; 
-parameter        MIPI_PMA_DIS_N                 = 1'b1 ;   
-parameter        PGA_BIAS_LANE0                 = 4'b1000 ;   
-parameter        PGA_BIAS_LANE1                 = 4'b1000 ;   
-parameter        PGA_BIAS_LANE2                 = 4'b1000 ;   
-parameter        PGA_BIAS_LANE3                 = 4'b1000 ;   
-parameter        PGA_BIAS_LANECK                = 4'b1000 ;   
-parameter        PGA_GAIN_LANE0                 = 4'b1000 ;   
-parameter        PGA_GAIN_LANE1                 = 4'b1000 ;   
-parameter        PGA_GAIN_LANE2                 = 4'b1000 ;   
-parameter        PGA_GAIN_LANE3                 = 4'b1000 ;   
-parameter        PGA_GAIN_LANECK                = 4'b1000 ;   
-parameter        RX_ODT_TRIM_LANE0              = 4'b1000 ;   
-parameter        RX_ODT_TRIM_LANE1              = 4'b1000 ;   
-parameter        RX_ODT_TRIM_LANE2              = 4'b1000 ;   
-parameter        RX_ODT_TRIM_LANE3              = 4'b1000 ;   
-parameter        RX_ODT_TRIM_LANECK             = 4'b1000 ;   
-parameter        SLEWN_CTL_LN0                  = 4'b1111 ;  
-parameter        SLEWN_CTL_LN1                  = 4'b1111 ;   
-parameter        SLEWN_CTL_LN2                  = 4'b1111 ;   
-parameter        SLEWN_CTL_LN3                  = 4'b1111 ;   
-parameter        SLEWN_CTL_LNCK                 = 4'b1111 ;   
-parameter        SLEWP_CTL_LN0                  = 4'b1111 ;   
-parameter        SLEWP_CTL_LN1                  = 4'b1111 ;   
-parameter        SLEWP_CTL_LN2                  = 4'b1111 ;   
-parameter        SLEWP_CTL_LN3                  = 4'b1111 ;   
-parameter        SLEWP_CTL_LNCK                 = 4'b1111 ;   
-parameter        STP_UNIT                       = 2'b01 ;  
-parameter        TERMN_CTL_LN0                  = 4'b1000 ;   
-parameter        TERMN_CTL_LN1                  = 4'b1000 ;   
-parameter        TERMN_CTL_LN2                  = 4'b1000 ;   
-parameter        TERMN_CTL_LN3                  = 4'b1000 ;   
-parameter        TERMN_CTL_LNCK                 = 4'b1000 ;   
-parameter        TERMP_CTL_LN0                  = 4'b1000 ;   
-parameter        TERMP_CTL_LN1                  = 4'b1000 ;   
-parameter        TERMP_CTL_LN2                  = 4'b1000 ;   
-parameter        TERMP_CTL_LN3                  = 4'b1000 ;   
-parameter        TERMP_CTL_LNCK                 = 4'b1000 ;   
-parameter        TEST_EN_LN0                    = 1'b0 ;   
-parameter        TEST_EN_LN1                    = 1'b0 ;   
-parameter        TEST_EN_LN2                    = 1'b0 ;   
-parameter        TEST_EN_LN3                    = 1'b0 ;   
-parameter        TEST_EN_LNCK                   = 1'b0 ;   
-parameter        TEST_N_IMP_LN0                 = 1'b0 ;   
-parameter        TEST_N_IMP_LN1                 = 1'b0 ;   
-parameter        TEST_N_IMP_LN2                 = 1'b0 ;   
-parameter        TEST_N_IMP_LN3                 = 1'b0 ;   
-parameter        TEST_N_IMP_LNCK                = 1'b0 ;   
-parameter        TEST_P_IMP_LN0                 = 1'b0 ;   
-parameter        TEST_P_IMP_LN1                 = 1'b0 ;   
-parameter        TEST_P_IMP_LN2                 = 1'b0 ;   
-parameter        TEST_P_IMP_LN3                 = 1'b0 ;   
-parameter        TEST_P_IMP_LNCK                = 1'b0 ;   
-endmodule
-
-module MIPI_CPHY (...);
-output [41:0] D0LN_HSRXD, D1LN_HSRXD, D2LN_HSRXD;
-output D0LN_HSRXD_VLD, D1LN_HSRXD_VLD, D2LN_HSRXD_VLD;
-output [1:0] D0LN_HSRX_DEMAP_INVLD, D1LN_HSRX_DEMAP_INVLD, D2LN_HSRX_DEMAP_INVLD;
-output D0LN_HSRX_FIFO_RDE_ERR, D0LN_HSRX_FIFO_WRF_ERR, D1LN_HSRX_FIFO_RDE_ERR, D1LN_HSRX_FIFO_WRF_ERR, D2LN_HSRX_FIFO_RDE_ERR, D2LN_HSRX_FIFO_WRF_ERR;
-output [1:0] D0LN_HSRX_WA, D1LN_HSRX_WA, D2LN_HSRX_WA;
-output D0LN_RX_CLK_1X_O, D1LN_RX_CLK_1X_O, D2LN_RX_CLK_1X_O;   
-output HSTX_FIFO_AE, HSTX_FIFO_AF;
-output HSTX_FIFO_RDE_ERR, HSTX_FIFO_WRF_ERR;
-output RX_CLK_MUXED;
-output TX_CLK_1X_O;
-output DI_LPRX0_A, DI_LPRX0_B, DI_LPRX0_C, DI_LPRX1_A, DI_LPRX1_B, DI_LPRX1_C, DI_LPRX2_A, DI_LPRX2_B, DI_LPRX2_C;
-output [7:0] MDRP_RDATA; 
-inout  D0A, D0B, D0C, D1A, D1B, D1C, D2A, D2B, D2C;
-input  D0LN_HSRX_EN, D0LN_HSTX_EN, D1LN_HSRX_EN, D1LN_HSTX_EN, D2LN_HSRX_EN, D2LN_HSTX_EN;
-input  [41:0] D0LN_HSTX_DATA,D1LN_HSTX_DATA, D2LN_HSTX_DATA;
-input  D0LN_HSTX_DATA_VLD, D1LN_HSTX_DATA_VLD, D2LN_HSTX_DATA_VLD;
-input  [1:0] D0LN_HSTX_MAP_DIS, D1LN_HSTX_MAP_DIS, D2LN_HSTX_MAP_DIS;
-input  D0LN_RX_CLK_1X_I,D1LN_RX_CLK_1X_I, D2LN_RX_CLK_1X_I;
-input  D0LN_RX_DRST_N, D0LN_TX_DRST_N, D1LN_RX_DRST_N, D1LN_TX_DRST_N, D2LN_RX_DRST_N, D2LN_TX_DRST_N;
-input  HSTX_ENLN0, HSTX_ENLN1, HSTX_ENLN2, LPTX_ENLN0, LPTX_ENLN1, LPTX_ENLN2;
-input  [7:0] MDRP_A_D_I;
-input  MDRP_A_INC_I;
-input  MDRP_CLK_I;
-input  [1:0] MDRP_OPCODE_I;
-input  PWRON_RX_LN0, PWRON_RX_LN1, PWRON_RX_LN2, PWRON_TX;
-input  ARST_RXLN0, ARST_RXLN1, ARST_RXLN2; 
-input  ARSTN_TX;
-input  RX_CLK_EN_LN0, RX_CLK_EN_LN1, RX_CLK_EN_LN2; 
-input  TX_CLK_1X_I;
-input  TXDP_ENLN0, TXDP_ENLN1, TXDP_ENLN2; 
-input  TXHCLK_EN; 
-input  DO_LPTX_A_LN0, DO_LPTX_A_LN1, DO_LPTX_A_LN2, DO_LPTX_B_LN0, DO_LPTX_B_LN1, DO_LPTX_B_LN2, DO_LPTX_C_LN0, DO_LPTX_C_LN1, DO_LPTX_C_LN2;
-input  GPLL_CK0,GPLL_CK90, GPLL_CK180, GPLL_CK270;
-input  HSRX_EN_D0, HSRX_EN_D1, HSRX_EN_D2; 
-input  HSRX_ODT_EN_D0, HSRX_ODT_EN_D1, HSRX_ODT_EN_D2;
-input  LPRX_EN_D0, LPRX_EN_D1, LPRX_EN_D2; 
-input  SPLL0_CKN, SPLL0_CKP, SPLL1_CKN, SPLL1_CKP;
-parameter TX_PLLCLK = "NONE"; 
-parameter D0LN_HS_TX_EN = 1'b1; 
-parameter D1LN_HS_TX_EN = 1'b1;
-parameter D2LN_HS_TX_EN = 1'b1;
-parameter D0LN_HS_RX_EN = 1'b1; 
-parameter D1LN_HS_RX_EN = 1'b1;
-parameter D2LN_HS_RX_EN = 1'b1;
-parameter TX_HS_21BIT_MODE = 1'b0; 
-parameter RX_OUTCLK_SEL = 2'b00; 
-parameter TX_W_LENDIAN = 1'b1; 
-parameter CLK_SEL = 2'b00; 
-parameter LNDIV_RATIO = 4'b0000; 
-parameter LNDIV_EN = 1'b0; 
-parameter D0LN_TX_REASGN_A = 2'b00; 
-parameter D0LN_TX_REASGN_B = 2'b01; 
-parameter D0LN_TX_REASGN_C = 2'b10; 
-parameter D0LN_RX_HS_21BIT_MODE = 1'b0; 
-parameter D0LN_RX_WA_SYNC_PAT0_EN = 1'b1;  
-parameter D0LN_RX_WA_SYNC_PAT0_H = 7'b1001001;  
-parameter D0LN_RX_WA_SYNC_PAT0_L = 8'b00100100;  
-parameter D0LN_RX_WA_SYNC_PAT1_EN = 1'b1;  
-parameter D0LN_RX_WA_SYNC_PAT1_H = 7'b0101001;  
-parameter D0LN_RX_WA_SYNC_PAT1_L = 8'b00100100;  
-parameter D0LN_RX_WA_SYNC_PAT2_EN = 1'b1;  
-parameter D0LN_RX_WA_SYNC_PAT2_H = 7'b0011001;  
-parameter D0LN_RX_WA_SYNC_PAT2_L = 8'b00100100;  
-parameter D0LN_RX_WA_SYNC_PAT3_EN = 1'b0;  
-parameter D0LN_RX_WA_SYNC_PAT3_H = 7'b0001001;  
-parameter D0LN_RX_WA_SYNC_PAT3_L = 8'b00100100;  
-parameter D0LN_RX_W_LENDIAN = 1'b1;  
-parameter D0LN_RX_REASGN_A = 2'b00; 
-parameter D0LN_RX_REASGN_B = 2'b01; 
-parameter D0LN_RX_REASGN_C = 2'b10; 
-parameter HSRX_LNSEL = 3'b111; 
-parameter EQ_RS_LN0 = 3'b001; 
-parameter EQ_CS_LN0 = 3'b101; 
-parameter PGA_GAIN_LN0 = 4'b0110; 
-parameter PGA_BIAS_LN0 = 4'b1000; 
-parameter EQ_PBIAS_LN0 = 4'b0100; 
-parameter EQ_ZLD_LN0 = 4'b1000; 
-parameter D1LN_TX_REASGN_A = 2'b00; 
-parameter D1LN_TX_REASGN_B = 2'b01; 
-parameter D1LN_TX_REASGN_C = 2'b10; 
-parameter D1LN_RX_HS_21BIT_MODE = 1'b0; 
-parameter D1LN_RX_WA_SYNC_PAT0_EN = 1'b1;  
-parameter D1LN_RX_WA_SYNC_PAT0_H = 7'b1001001;  
-parameter D1LN_RX_WA_SYNC_PAT0_L = 8'b00100100;  
-parameter D1LN_RX_WA_SYNC_PAT1_EN = 1'b1;  
-parameter D1LN_RX_WA_SYNC_PAT1_H = 7'b0101001;  
-parameter D1LN_RX_WA_SYNC_PAT1_L = 8'b00100100;  
-parameter D1LN_RX_WA_SYNC_PAT2_EN = 1'b1;  
-parameter D1LN_RX_WA_SYNC_PAT2_H = 7'b0011001;  
-parameter D1LN_RX_WA_SYNC_PAT2_L = 8'b00100100;  
-parameter D1LN_RX_WA_SYNC_PAT3_EN = 1'b0;  
-parameter D1LN_RX_WA_SYNC_PAT3_H = 7'b0001001;  
-parameter D1LN_RX_WA_SYNC_PAT3_L = 8'b00100100;  
-parameter D1LN_RX_W_LENDIAN = 1'b1;  
-parameter D1LN_RX_REASGN_A = 2'b00; 
-parameter D1LN_RX_REASGN_B = 2'b01; 
-parameter D1LN_RX_REASGN_C = 2'b10; 
-parameter EQ_RS_LN1 = 3'b001; 
-parameter EQ_CS_LN1 = 3'b101; 
-parameter PGA_GAIN_LN1 = 4'b0110; 
-parameter PGA_BIAS_LN1 = 4'b1000; 
-parameter EQ_PBIAS_LN1 = 4'b0100; 
-parameter EQ_ZLD_LN1 = 4'b1000; 
-parameter D2LN_TX_REASGN_A = 2'b00; 
-parameter D2LN_TX_REASGN_B = 2'b01; 
-parameter D2LN_TX_REASGN_C = 2'b10; 
-parameter D2LN_RX_HS_21BIT_MODE = 1'b0; 
-parameter D2LN_RX_WA_SYNC_PAT0_EN = 1'b1;  
-parameter D2LN_RX_WA_SYNC_PAT0_H = 7'b1001001;  
-parameter D2LN_RX_WA_SYNC_PAT0_L = 8'b00100100;  
-parameter D2LN_RX_WA_SYNC_PAT1_EN = 1'b1;  
-parameter D2LN_RX_WA_SYNC_PAT1_H = 7'b0101001;  
-parameter D2LN_RX_WA_SYNC_PAT1_L = 8'b00100100;  
-parameter D2LN_RX_WA_SYNC_PAT2_EN = 1'b1;  
-parameter D2LN_RX_WA_SYNC_PAT2_H = 7'b0011001;  
-parameter D2LN_RX_WA_SYNC_PAT2_L = 8'b00100100;  
-parameter D2LN_RX_WA_SYNC_PAT3_EN = 1'b0;  
-parameter D2LN_RX_WA_SYNC_PAT3_H = 7'b0001001;  
-parameter D2LN_RX_WA_SYNC_PAT3_L = 8'b00100100;  
-parameter D2LN_RX_W_LENDIAN = 1'b1;  
-parameter D2LN_RX_REASGN_A = 2'b00; 
-parameter D2LN_RX_REASGN_B = 2'b01; 
-parameter D2LN_RX_REASGN_C = 2'b10; 
-parameter EQ_RS_LN2 = 3'b001; 
-parameter EQ_CS_LN2 = 3'b101; 
-parameter PGA_GAIN_LN2 = 4'b0110; 
-parameter PGA_BIAS_LN2 = 4'b1000; 
-parameter EQ_PBIAS_LN2 = 4'b0100; 
-parameter EQ_ZLD_LN2 = 4'b1000; 
-endmodule
-
 module GTR12_QUAD (...);
 endmodule
 
@@ -2651,18 +1926,6 @@ endmodule
 module GTR12_PMAC (...);
 endmodule
 
-module GTR12_QUADA (...);
-endmodule
-
-module GTR12_UPARA (...);
-endmodule
-
-module GTR12_PMACA (...);
-endmodule
-
-module GTR12_QUADB (...);
-endmodule
-
 module DQS (...);
 input DQSIN,PCLK,FCLK,RESET;
 input [3:0] READ;
@@ -2678,3 +1941,4 @@ parameter RD_PNTR = 3'b000;
 parameter DQS_MODE = "X1"; 
 parameter HWL = "false";   
 endmodule
+

techlibs/ice40/ice40_dsp.pmg

@@ -46,17 +46,24 @@ code sigA sigB sigH
 
 	// Only care about those bits that are used
 	int i;
-	for (i = 0; i < GetSize(O); i++) {
-		if (nusers(O[i]) <= 1)
-			break;
-		sigH.append(O[i]);
-	}
+	for (i = GetSize(O) - 1; i > 0 && nusers(O[i]) <= 1; i--)
+		;
 	// This sigM could have no users if downstream sinks (e.g. $add) is
 	//   narrower than $mul result, for example
 	if (i == 0)
 		reject;
 
-	log_assert(nusers(O.extract_end(i)) <= 1);
+	for (int j = 0, wire_width = 0; j <= i; j++) 
+		if (nusers(O[j]) == 0)
+			wire_width++;
+		else {
+			if (wire_width) { // add empty wires for bit offset if needed
+				sigH.append(module->addWire(NEW_ID, wire_width));
+				wire_width = 0;
+			}
+			sigH.append(O[j]);
+		}
+
 endcode
 
 code argQ ffA sigA clock clock_pol

techlibs/xilinx/cells_map.v

@@ -187,7 +187,10 @@ module \$__XILINX_SHIFTX (A, B, Y);
     // Trim off any leading 1'bx -es in A
     else if (_TECHMAP_CONSTMSK_A_[A_WIDTH-1] && _TECHMAP_CONSTVAL_A_[A_WIDTH-1] === 1'bx) begin
       localparam A_WIDTH_new = A_WIDTH_trimmed(A_WIDTH-1);
-      \$__XILINX_SHIFTX  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(A_WIDTH_new), .B_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(A[A_WIDTH_new-1:0]), .B(B), .Y(Y));
+      if (A_WIDTH_new == 0)
+        assign Y = 1'bx;
+      else
+        \$__XILINX_SHIFTX  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(A_WIDTH_new), .B_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(A[A_WIDTH_new-1:0]), .B(B), .Y(Y));
     end
     else if (A_WIDTH < `MIN_MUX_INPUTS) begin
       wire _TECHMAP_FAIL_ = 1;

tests/alumacc/basic.ys

@@ -0,0 +1,61 @@
+read_verilog <<EOF
+module gate(input signed [2:0] a1, input signed [2:0] b1,
+			input [1:0] a2, input [3:0] b2, input c, input d, output signed [3:0] y);
+  wire signed [3:0] ab1;
+  assign ab1 = a1 * b1;
+  assign y = ab1 + a2*b2 + c + d + 1;
+endmodule
+EOF
+prep
+equiv_opt -assert alumacc
+design -load postopt
+stat
+design -save save
+equiv_opt -assert maccmap
+design -load save
+equiv_opt -assert maccmap -unmap
+
+design -reset
+read_verilog <<EOF
+module gate(input signed [2:0] a1, input signed [1:0] b1, output signed [3:0] y);
+  assign y = a1 * b1;
+endmodule
+EOF
+prep
+equiv_opt -assert alumacc
+design -load postopt
+stat
+design -save save
+equiv_opt -assert maccmap
+design -load save
+equiv_opt -assert maccmap -unmap
+
+design -reset
+read_verilog <<EOF
+module gate(input [2:0] a, input [1:0] b, output [3:0] y);
+  assign y = a * b;
+endmodule
+EOF
+prep
+equiv_opt -assert alumacc
+design -load postopt
+stat
+design -save save
+equiv_opt -assert maccmap
+design -load save
+equiv_opt -assert maccmap -unmap
+
+design -reset
+read_verilog <<EOF
+module gate(input [2:0] a, input [1:0] b, input [1:0] c, output [3:0] y);
+  assign y = a * b - c;
+endmodule
+EOF
+prep
+equiv_opt -assert alumacc
+design -load postopt
+stat
+design -save save
+equiv_opt -assert maccmap
+design -load save
+equiv_opt -assert maccmap -unmap

tests/alumacc/macc_infer_n_unmap.ys

@@ -0,0 +1,19 @@
+read_verilog <<EOF
+module gate(input signed [2:0] a1, input signed [2:0] b1,
+			input [1:0] a2, input [3:0] b2, input c, input d, output signed [3:0] y);
+  wire signed [3:0] ab1;
+  assign ab1 = a1 * b1;
+  assign y = ab1 + a2*b2 + c + d + 1;
+endmodule
+EOF
+prep
+
+design -save gold
+alumacc
+opt_clean
+select -assert-count 1 t:$macc_v2
+maccmap -unmap
+design -copy-from gold -as gold gate
+equiv_make gold gate equiv
+equiv_induct equiv
+equiv_status -assert equiv

tests/cxxrtl/test_value_fuzz.cc

@@ -241,7 +241,10 @@ struct CtlzTest
 	{
 		if (a == 0)
 			return bits;
-		return __builtin_clzl(a) - (64 - bits);
+		if (sizeof(long) == 4)
+			return __builtin_clzll(a) - (64 - bits);
+		else
+			return __builtin_clzl(a) - (64 - bits);
 	}
 
 	template<size_t Bits>

tests/gen-tests-makefile.sh

@@ -17,20 +17,20 @@ generate_target() {
 generate_ys_test() {
 	ys_file=$1
 	yosys_args_=${2:-}
-	generate_target "$ys_file" "\"$YOSYS_BASEDIR/yosys\" -ql ${ys_file%.*}.log $yosys_args_ $ys_file"
+	generate_target "$ys_file" "\"$YOSYS_BASEDIR/yosys\" -ql ${ys_file}.err $yosys_args_ $ys_file && mv ${ys_file}.err ${ys_file}.log"
 }
 
 # $ generate_tcl_test tcl_file [yosys_args]
 generate_tcl_test() {
 	tcl_file=$1
 	yosys_args_=${2:-}
-	generate_target "$tcl_file" "\"$YOSYS_BASEDIR/yosys\" -ql ${tcl_file%.*}.log $yosys_args_ $tcl_file"
+	generate_target "$tcl_file" "\"$YOSYS_BASEDIR/yosys\" -ql ${tcl_file}.err $yosys_args_ $tcl_file && mv ${tcl_file}.err ${tcl_file}.log"
 }
 
 # $ generate_bash_test bash_file
 generate_bash_test() {
 	bash_file=$1
-	generate_target "$bash_file" "bash -v $bash_file >${bash_file%.*}.log 2>&1"
+	generate_target "$bash_file" "bash -v $bash_file >${bash_file}.err 2>&1 && mv ${bash_file}.err ${bash_file}.log"
 }
 
 # $ generate_tests [-y|--yosys-scripts] [-s|--prove-sv] [-b|--bash] [-a|--yosys-args yosys_args]

tests/liberty/libcache.ys

@@ -0,0 +1,58 @@
+libcache -enable busdef.lib
+
+logger -expect log "Caching is disabled by default." 1
+logger -expect log "Caching is enabled for `busdef.lib'." 1
+libcache -list
+logger -check-expected
+
+logger -expect log "Caching data" 1
+log Caching data
+read_liberty normal.lib; design -reset
+logger -check-expected
+
+logger -expect log "Caching data" 1
+read_liberty -lib busdef.lib; design -reset
+logger -check-expected
+
+logger -expect log "Using caching data" 1
+log Using caching data
+read_liberty normal.lib; design -reset
+logger -check-expected
+
+logger -expect log "Using cached data" 1
+read_liberty -lib busdef.lib; design -reset
+logger -check-expected
+
+libcache -purge busdef.lib
+
+logger -expect log "Caching is disabled by default." 1
+logger -expect log "Caching is enabled for `busdef.lib'." 1
+log Caching is enabled for `busdef.lib'.
+libcache -list
+logger -check-expected
+
+libcache -enable -all
+
+logger -expect log "Caching is enabled by default." 1
+libcache -list
+logger -check-expected
+
+logger -expect log "Caching data" 1
+read_liberty normal.lib; design -reset
+logger -check-expected
+
+logger -expect log "Caching data" 1
+read_liberty -lib busdef.lib; design -reset
+logger -check-expected
+
+logger -expect log "Using cached data" 1
+read_liberty -lib busdef.lib; design -reset
+logger -check-expected
+
+logger -expect log "Using cached data" 1
+read_liberty normal.lib; design -reset
+logger -check-expected
+
+logger -expect log "Using cached data" 1
+dfflibmap -liberty normal.lib
+logger -check-expected

tests/opt/opt_expr_more.ys

@@ -0,0 +1,177 @@
+design -reset
+read_verilog <<EOT
+module test(input a, output [7:0] y);
+assign y = a * 0;
+endmodule
+EOT
+
+equiv_opt -assert opt_expr -fine
+design -load postopt
+# The multiplication by zero should be replaced with constant zero
+select -assert-count 0 t:$mul
+
+## opt.opt_expr.mul_shift
+
+design -reset
+read_verilog <<EOT
+module test(input [7:0] a, output [15:0] y, output [15:0] z);
+assign y = a * 8; // Multiply by 2^3 (power of 2)
+assign z = 8 * a;
+endmodule
+EOT
+
+equiv_opt -assert opt_expr -fine
+design -load postopt
+# The multiplication by 8 should be replaced with a shift by const
+select -assert-count 0 t:$mul
+# No shift operator cells should be present
+select -assert-count 0 t:$shl
+
+design -reset
+read_verilog <<EOT
+module test(input [7:0] a, output [7:0] y);
+assign y = a / 4; // Division by 2^2 (power of 2)
+endmodule
+EOT
+
+equiv_opt -assert opt_expr -fine
+design -load postopt
+# The division by 4 should be replaced with a shift by const
+select -assert-count 0 t:$div
+
+design -reset
+read_verilog <<EOT
+module test(input [7:0] a, output [7:0] y);
+assign y = a / 0; // Division by zero should be replaced with x
+endmodule
+EOT
+
+opt_expr -fine
+# The division by zero should be removed
+select -assert-count 0 t:$div
+# No cells should be left as it's replaced with constant undef
+select -assert-none t:*
+
+design -reset
+read_verilog <<EOT
+module test(input s, output y);
+assign y = s ? 1'b1 : 1'b0; // This is equivalent to just 's'
+endmodule
+EOT
+
+equiv_opt -assert opt_expr -fine -mux_bool
+design -load postopt
+# The mux should be removed completely
+select -assert-count 0 t:$mux
+# No additional cells needed - direct connection
+select -assert-none t:*
+
+design -reset
+read_verilog <<EOT
+module test(input s, output y);
+assign y = s ? 1'b0 : 1'b1; // This is equivalent to '!s'
+endmodule
+EOT
+
+equiv_opt -assert opt_expr -fine -mux_bool
+design -load postopt
+# The mux should be converted to a not gate
+select -assert-count 0 t:$mux
+select -assert-count 1 t:$not
+
+design -reset
+read_verilog <<EOT
+module test(input [3:0] a, input [3:0] b, output y);
+assign y = (a == b); // Test equality optimization
+endmodule
+EOT
+
+equiv_opt -assert opt_expr -fine
+design -load postopt
+# Check for optimization of equality comparison
+select -assert-count 1 t:$eq
+
+# opt.opt_expr.eqneq.*
+
+design -reset
+read_verilog -noopt <<EOT
+module test(output y1, y2, y3, y4);
+// Compare two constants that are guaranteed to be different
+assign y1 = 2'b01 == 2'b10;
+assign y2 = 2'b01 != 2'b10;
+assign y3 = 2'b01 !== 2'b10;
+assign y4 = 2'b01 === 2'b10;
+endmodule
+EOT
+
+equiv_opt -assert opt_expr
+select -assert-count 1 t:$eq
+design -load postopt
+# The comparison of different constants should be replaced with constant 0
+select -assert-count 0 t:$eq
+# No other cells should be present (just the constant driver)
+select -assert-none t:*
+
+# opt.opt_expr.invert.double
+
+design -reset
+read_verilog -noopt <<EOT
+module test(input a, output y);
+// Double negation should be optimized away
+wire not_a;
+assign not_a = ~a;
+assign y = ~not_a;
+endmodule
+EOT
+
+equiv_opt -assert opt_expr
+select -assert-count 2 t:$not
+design -load postopt
+# Both NOT gates should be eliminated
+opt_clean -purge
+select -assert-count 0 t:$not
+# No other cells should be present
+select -assert-none t:*
+
+# opt.opt_expr.reduce_xnor_not
+
+design -reset
+read_verilog -noopt <<EOT
+module test(input a, output y);
+assign y = ~^a; // XNOR reduction of a single bit
+endmodule
+EOT
+
+equiv_opt -assert opt_expr -full
+design -load postopt
+select -assert-count 0 t:$reduce_xnor
+select -assert-count 1 t:$not
+
+## opt.opt_expr.mod_mask
+
+design -reset
+read_verilog -noopt <<EOT
+module test(input [7:0] a, output [7:0] y);
+assign y = a % 8; // Modulo by power of 2
+endmodule
+EOT
+
+select -assert-count 1 t:$mod
+equiv_opt -assert opt_expr -full
+design -load postopt
+select -assert-count 0 t:$mod
+select -assert-count 0 t:$and
+
+## opt.opt_expr.eqneq.empty (indirectly)
+
+design -reset
+read_verilog -noopt <<EOT
+module test(output [7:0] y1);
+assign y1 = 7'b1 == 7'b1;
+endmodule
+EOT
+
+select -assert-count 1 t:$eq
+equiv_opt -assert opt_expr -full
+design -load postopt
+select -assert-count 0 t:$eq

tests/opt/opt_expr_mux_undef.ys

@@ -0,0 +1,290 @@
+
+read_rtlil <<EOT
+module \uut
+  wire output 1 \out
+  wire input 2 width 16 \in
+  wire input 3 width 4 \sel
+  cell $_MUX16_ \mux
+    connect \A \in [0]
+    connect \B \in [1]
+    connect \C \in [2]
+    connect \D \in [3]
+    connect \E \in [4]
+    connect \F \in [5]
+    connect \G \in [6]
+    connect \H \in [7]
+    connect \I \in [8]
+    connect \J \in [9]
+    connect \K \in [10]
+    connect \L \in [11]
+    connect \M \in [12]
+    connect \N \in [13]
+    connect \O \in [14]
+    connect \P \in [15]
+    connect \S \sel [0]
+    connect \T \sel [1]
+    connect \U \sel [2]
+    connect \V \sel [3]
+    connect \Y \out
+  end
+end
+EOT
+
+##########
+# all undef
+# no mux
+# output undef
+
+design -reset
+read_rtlil <<EOT
+module \uut
+  wire output 1 \out
+  cell $mux \mux
+    parameter \WIDTH 1
+    connect \A 1'x
+    connect \B 1'x
+    connect \S 1'x
+    connect \Y \out
+  end
+end
+EOT
+
+opt_expr -mux_undef
+select -assert-none t:$mux
+select -assert-count 1 o:out %ci*
+
+##
+
+design -reset
+read_rtlil <<EOT
+module \uut
+  wire output 1 \out
+  cell $_MUX_ \mux
+    connect \A 1'x
+    connect \B 1'x
+    connect \S 1'x
+    connect \Y \out
+  end
+end
+EOT
+
+opt_expr -mux_undef
+select -assert-none t:$_MUX_
+select -assert-count 1 o:out %ci*
+
+##
+
+design -reset
+read_rtlil <<EOT
+module \uut
+  wire output 1 \out
+  cell $_MUX4_ \mux
+    connect \A 1'x
+    connect \B 1'x
+    connect \C 1'x
+    connect \D 1'x
+    connect \S 1'x
+    connect \T 1'x
+    connect \Y \out
+  end
+end
+EOT
+
+opt_expr -mux_undef
+select -assert-none t:$_MUX4_
+
+##
+
+design -reset
+read_rtlil <<EOT
+module \uut
+  wire output 1 \out
+  cell $_MUX8_ \mux
+    connect \A 1'x
+    connect \B 1'x
+    connect \C 1'x
+    connect \D 1'x
+    connect \E 1'x
+    connect \F 1'x
+    connect \G 1'x
+    connect \H 1'x
+    connect \S 1'x
+    connect \T 1'x
+    connect \U 1'x
+    connect \Y \out
+  end
+end
+EOT
+
+opt_expr -mux_undef
+select -assert-none t:$_MUX8_
+
+##
+
+design -reset
+read_rtlil <<EOT
+module \uut
+  wire output 1 \out
+  cell $_MUX16_ \mux
+    connect \A 1'x
+    connect \B 1'x
+    connect \C 1'x
+    connect \D 1'x
+    connect \E 1'x
+    connect \F 1'x
+    connect \G 1'x
+    connect \H 1'x
+    connect \I 1'x
+    connect \J 1'x
+    connect \K 1'x
+    connect \L 1'x
+    connect \M 1'x
+    connect \N 1'x
+    connect \O 1'x
+    connect \P 1'x
+    connect \S 1'x
+    connect \T 1'x
+    connect \U 1'x
+    connect \V 1'x
+    connect \Y \out
+  end
+end
+EOT
+
+opt_expr -mux_undef
+select -assert-none t:$_MUX16_
+
+##########
+# a and b undef
+# no mux
+# output undef
+
+design -reset
+read_rtlil <<EOT
+module \uut
+  wire output 1 \out
+  wire input 3 \sel
+  cell $mux \mux
+    parameter \WIDTH 1
+    connect \A 1'x
+    connect \B 1'x
+    connect \S \sel
+    connect \Y \out
+  end
+end
+EOT
+
+opt_expr -mux_undef
+select -assert-none t:$mux
+select -assert-count 1 o:out %ci*
+
+##
+
+design -reset
+read_rtlil <<EOT
+module \uut
+  wire output 1 \out
+  wire input 3 \sel
+  cell $_MUX_ \mux
+    connect \A 1'x
+    connect \B 1'x
+    connect \S \sel
+    connect \Y \out
+  end
+end
+EOT
+
+opt_expr -mux_undef
+select -assert-none t:$_MUX_
+select -assert-count 1 o:out %ci*
+
+##
+
+design -reset
+read_rtlil <<EOT
+module \uut
+  wire output 1 \out
+  wire input 3 width 2 \sel
+  cell $_MUX4_ \mux
+    connect \A 1'x
+    connect \B 1'x
+    connect \C 1'x
+    connect \D 1'x
+    connect \S \sel [0]
+    connect \T \sel [1]
+    connect \Y \out
+  end
+end
+EOT
+
+opt_expr -mux_undef
+select -assert-none t:$_MUX4_
+select -assert-count 1 o:out %ci*
+
+##
+
+design -reset
+read_rtlil <<EOT
+module \uut
+  wire output 1 \out
+  wire input 3 width 3 \sel
+  cell $_MUX8_ \mux
+    connect \A 1'x
+    connect \B 1'x
+    connect \C 1'x
+    connect \D 1'x
+    connect \E 1'x
+    connect \F 1'x
+    connect \G 1'x
+    connect \H 1'x
+    connect \S \sel [0]
+    connect \T \sel [1]
+    connect \U \sel [2]
+    connect \Y \out
+  end
+end
+EOT
+
+opt_expr -mux_undef
+select -assert-none t:$_MUX8_
+select -assert-count 1 o:out %ci*
+
+##
+
+design -reset
+read_rtlil <<EOT
+module \uut
+  wire output 1 \out
+  wire input 3 width 4 \sel
+  cell $_MUX16_ \mux
+    connect \A 1'x
+    connect \B 1'x
+    connect \C 1'x
+    connect \D 1'x
+    connect \E 1'x
+    connect \F 1'x
+    connect \G 1'x
+    connect \H 1'x
+    connect \I 1'x
+    connect \J 1'x
+    connect \K 1'x
+    connect \L 1'x
+    connect \M 1'x
+    connect \N 1'x
+    connect \O 1'x
+    connect \P 1'x
+    connect \S \sel [0]
+    connect \T \sel [1]
+    connect \U \sel [2]
+    connect \V \sel [3]
+    connect \Y \out
+  end
+end
+EOT
+
+opt_expr -mux_undef
+select -assert-none t:$_MUX16_
+select -assert-count 1 o:out %ci*
+
+##########
+

tests/opt/opt_merge_basic.ys

@@ -0,0 +1,166 @@
+read_verilog <<EOT
+module top(A, B, X, Y);
+input [7:0] A, B;
+output [7:0] X, Y;
+assign X = A + B;
+assign Y = A + B;
+endmodule
+EOT
+# Most basic case
+# Binary
+select -assert-count 2 t:$add
+equiv_opt -assert opt_merge
+design -load postopt
+select -assert-count 1 t:$add
+
+design -reset
+read_verilog <<EOT
+module top(A, B, C, X, Y);
+input [7:0] A, B, C;
+output [7:0] X, Y;
+assign X = A + B;
+assign Y = A + C; // <- look here
+endmodule
+EOT
+# Reject on a different input
+select -assert-count 2 t:$add
+opt_merge
+select -assert-count 2 t:$add
+
+design -reset
+read_verilog <<EOT
+module top(A, X, Y);
+input [7:0] A;
+output X, Y;
+assign X = ^A;
+assign Y = ^A;
+endmodule
+EOT
+# Unary
+select -assert-count 2 t:$reduce_xor
+dump
+opt_merge
+select -assert-count 1 t:$reduce_xor
+
+design -reset
+read_verilog -icells <<EOT
+module top(A, B, X, Y);
+input [7:0] A, B;
+output X, Y;
+  \$reduce_xor  #(
+    .A_SIGNED(32'd0),
+    .A_WIDTH(32'd16),
+    .Y_WIDTH(32'd1),
+  ) one  (
+    .A({A, B}), // <- look here
+    .Y(X)
+  );
+  \$reduce_xor  #(
+    .A_SIGNED(32'd0),
+    .A_WIDTH(32'd16),
+    .Y_WIDTH(32'd1),
+  ) other  (
+    .A({B, A}), // <- look here
+    .Y(Y)
+  );
+endmodule
+EOT
+# Unary is sorted
+opt_expr
+select -assert-count 2 t:$reduce_xor
+equiv_opt -assert opt_merge
+design -load postopt
+select -assert-count 1 t:$reduce_xor
+
+design -reset
+read_verilog -icells <<EOT
+module top(A, B, X, Y);
+input [7:0] A, B;
+output X, Y;
+  \$reduce_or  #(
+    .A_SIGNED(32'd0),
+    .A_WIDTH(32'd24),
+    .Y_WIDTH(32'd1),
+  ) one  (
+    .A({A, B, B}), // <- look here
+    .Y(X)
+  );
+  \$reduce_or  #(
+    .A_SIGNED(32'd0),
+    .A_WIDTH(32'd24),
+    .Y_WIDTH(32'd1),
+  ) other  (
+    .A({A, A, B}), // <- look here
+    .Y(Y)
+  );
+endmodule
+EOT
+# Unary is unified when valid
+opt_expr
+select -assert-count 2 t:$reduce_or
+equiv_opt -assert opt_merge
+design -load postopt
+select -assert-count 1 t:$reduce_or
+
+design -reset
+read_verilog -icells <<EOT
+module top(A, B, X, Y);
+input [7:0] A, B;
+output X, Y;
+  \$reduce_xor  #(
+    .A_SIGNED(32'd0),
+    .A_WIDTH(32'd24),
+    .Y_WIDTH(32'd1),
+  ) one  (
+    .A({A, B, B}), // <- look here
+    .Y(X)
+  );
+  \$reduce_xor  #(
+    .A_SIGNED(32'd0),
+    .A_WIDTH(32'd24),
+    .Y_WIDTH(32'd1),
+  ) other  (
+    .A({A, A, B}), // <- look here
+    .Y(Y)
+  );
+endmodule
+EOT
+# Unary isn't unified when that would be invalid
+opt_expr
+select -assert-count 2 t:$reduce_xor
+equiv_opt -assert opt_merge
+design -load postopt
+select -assert-count 2 t:$reduce_xor
+
+# TODO pmux
+
+design -reset
+read_verilog <<EOT
+module top(A, B, X, Y);
+input [7:0] A, B;
+output X, Y;
+assign X = A > B;
+assign Y = A > B;
+endmodule
+EOT
+# Exercise the general case in hash_cell_inputs - accept
+opt_expr
+select -assert-count 2 t:$gt
+equiv_opt -assert opt_merge
+design -load postopt
+select -assert-count 1 t:$gt
+
+design -reset
+read_verilog <<EOT
+module top(A, B, C, X, Y);
+input [7:0] A, B, C;
+output X, Y;
+assign X = A > B;
+assign Y = A > C; // <- look here
+endmodule
+EOT
+# Exercise the general case in hash_cell_inputs - reject
+opt_expr
+select -assert-count 2 t:$gt
+opt_merge
+select -assert-count 2 t:$gt

tests/opt/opt_pow.ys

@@ -0,0 +1,89 @@
+# Default power of two
+
+design -reset
+
+read_rtlil << EOT
+autoidx 3
+attribute \cells_not_processed 1
+attribute \src "<stdin>:1.1-3.10"
+module \top
+  attribute \src "<stdin>:2.17-2.20"
+  wire width 32 $add$<stdin>:2$1_Y
+  attribute \src "<stdin>:2.12-2.21"
+  wire width 32 signed $pow$<stdin>:2$2_Y
+  attribute \src "<stdin>:1.29-1.30"
+  wire width 15 input 1 \a
+  attribute \src "<stdin>:1.51-1.52"
+  wire width 32 output 2 \b
+  attribute \src "<stdin>:2.17-2.20"
+  cell $add $add$<stdin>:2$1
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 15
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 32
+    parameter \Y_WIDTH 32
+    connect \A \a
+    connect \B 2
+    connect \Y $add$<stdin>:2$1_Y
+  end
+  attribute \src "<stdin>:2.12-2.21"
+  cell $pow $pow$<stdin>:2$2
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 32
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 32
+    parameter \Y_WIDTH 32
+    connect \A 2
+   connect \B $add$<stdin>:2$1_Y
+    connect \Y $pow$<stdin>:2$2_Y
+  end
+  connect \b $pow$<stdin>:2$2_Y
+end
+EOT
+
+select -assert-count 1 t:$pow
+select -assert-none t:$shl
+opt_expr
+select -assert-none t:$pow
+select -assert-count 1 t:$shl
+
+read_verilog << EOT
+module ref(input wire [14:0] a, output wire [31:0] b);
+assign b = 1 << (a+2);
+endmodule
+EOT
+
+equiv_make top ref equiv
+select -assert-any -module equiv t:$equiv
+equiv_induct
+equiv_status -assert
+
+# Other power of 2 value
+
+design -reset
+
+read_verilog <<EOT
+module top(input wire [14:0] a, output wire [31:0] b);
+assign b = 128**(a+2);
+endmodule
+EOT
+
+# Check the cell counts have changed correctly
+select -assert-count 1 t:$pow
+select -assert-none t:$shl
+select -assert-none t:$mul
+opt_expr
+select -assert-none t:$pow
+select -assert-count 1 t:$shl
+select -assert-count 1 t:$mul
+
+read_verilog <<EOT
+module ref(input wire [14:0] a, output wire [31:0] b);
+assign b = 1 << (7 * (a+2));
+endmodule
+EOT
+
+equiv_make top ref equiv
+select -assert-any -module equiv t:$equiv
+equiv_induct
+equiv_status -assert

tests/various/bug4865.ys

@@ -0,0 +1,70 @@
+read_rtlil << EOF
+
+
+autoidx 524
+
+attribute \top 1
+attribute \library "work"
+attribute \hdlname "main"
+module \main
+
+  attribute \force_downto 1
+  wire width 18 $verific$mult_4$garbage/usb.v:12$388.etc.blk.partial[0]
+
+  wire width 12 $delete_wire$514
+
+  wire width 4 $test
+  
+  attribute \module_not_derived 1
+  cell \SB_MAC16 $verific$mult_4$garbage/usb.v:12$388.etc.sliceB[0].mul
+    parameter \A_REG 1'0
+    parameter \A_SIGNED 0
+    parameter \BOTADDSUB_CARRYSELECT 2'00
+    parameter \BOTADDSUB_LOWERINPUT 2'00
+    parameter \BOTADDSUB_UPPERINPUT 1'0
+    parameter \BOTOUTPUT_SELECT 2'11
+    parameter \BOT_8x8_MULT_REG 1'0
+    parameter \B_REG 1'0
+    parameter signed \B_SIGNED 0
+    parameter \C_REG 1'0
+    parameter \D_REG 1'0
+    parameter \MODE_8x8 1'0
+    parameter \NEG_TRIGGER 1'0
+    parameter \PIPELINE_16x16_MULT_REG1 1'0
+    parameter \PIPELINE_16x16_MULT_REG2 1'0
+    parameter \TOPADDSUB_CARRYSELECT 2'00
+    parameter \TOPADDSUB_LOWERINPUT 2'00
+    parameter \TOPADDSUB_UPPERINPUT 1'0
+    parameter \TOPOUTPUT_SELECT 2'11
+    parameter \TOP_8x8_MULT_REG 1'0
+    connect \A 16'x
+    connect \B 16'x
+    connect \O {  $test $delete_wire$514 14'x $verific$mult_4$garbage/usb.v:12$388.etc.blk.partial[0] [1:0] }
+  end
+
+  cell $add $techmap$verific$mult_4$garbage/usb.v:12$388.etc.sliceA.last.$add$/home/emil/pulls/yosys/share/mul2dsp.v:216$483
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 18
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 2
+    parameter \Y_WIDTH 19
+    connect \A 18'x
+    connect \B $verific$mult_4$garbage/usb.v:12$388.etc.blk.partial[0] [1:0]
+    connect \Y 19'x
+  end
+
+  cell $add $techmap$verific$mult_4$garbage/usb.v:12$388.$add$/home/emil/pulls/yosys/share/mul2dsp.v:173$480
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 2
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 2
+    parameter \Y_WIDTH 2
+    connect \A $delete_wire$514 [1:0]
+    connect \B 2'x
+    connect \Y 2'x
+  end
+
+end
+EOF
+
+ice40_dsp

tests/various/bug4909.ys

@@ -0,0 +1,44 @@
+read_rtlil << EOF
+autoidx 20
+attribute \src "3510.v:2.1-26.10"
+attribute \cells_not_processed 1
+attribute \tamara_triplicate 1
+module \top
+  attribute \src "3510.v:14.3-17.8"
+  wire width 4 $0\reg5[3:0]
+  attribute $bugpoint 1
+  wire width 4 $auto$bugpoint.cc:258:simplify_something$12
+  wire $delete_wire$14
+  attribute \src "3510.v:13.19-13.59"
+  wire width 4 $xnor$3510.v:13$1_Y
+  attribute \src "3510.v:11.23-11.27"
+  wire width 4 \reg5
+  attribute \src "3510.v:8.24-8.29"
+  wire width 3 \wire4
+  attribute \src "3510.v:3.33-3.34"
+  wire width 12 output 1 \y
+  attribute \src "3510.v:13.19-13.59"
+  cell $xnor $xnor$3510.v:13$1
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 3
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 4
+    parameter \Y_WIDTH 4
+    connect \A 3'x
+    connect \B $auto$bugpoint.cc:258:simplify_something$12
+    connect \Y $xnor$3510.v:13$1_Y
+  end
+  attribute \src "3510.v:14.3-17.8"
+  process $proc$3510.v:14$2
+    assign $0\reg5[3:0] { \wire4 [2] \wire4 }
+    sync posedge $delete_wire$14
+      update \reg5 $0\reg5[3:0]
+  end
+  connect \y [4:0] { \reg5 1'0 }
+  connect \wire4 $xnor$3510.v:13$1_Y [2:0]
+end
+EOF
+
+prep
+splitcells
+

tests/various/setundef.sv

@@ -0,0 +1,10 @@
+module foo #(parameter [1:0] a) (output [1:0] o);
+	assign o = a;
+endmodule
+
+module top(output [1:0] o);
+	foo #(2'b0x) foo(o);
+	always_comb begin
+		assert(o == 2'b00);
+	end
+endmodule

tests/various/setundef.ys

@@ -0,0 +1,8 @@
+read_verilog -sv setundef.sv
+setundef -zero -params
+hierarchy -top top
+flatten
+proc
+async2sync
+write_json
+sat -seq 5 -prove-asserts

tests/various/stat.ys

@@ -0,0 +1,14 @@
+read_rtlil << EOF
+module \top
+  wire input 1 \A
+  wire output 2 \Y
+  cell \sg13g2_and2_1 \sub
+    connect \A \A
+    connect \B 1'0
+    connect \Y \Y
+  end
+end
+EOF
+logger -expect log "Chip area for module '\\top': 9.072000" 1
+logger -expect-no-warnings
+stat -liberty ../../tests/liberty/foundry_data/sg13g2_stdcell_typ_1p20V_25C.lib.filtered.gz