mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2026-07-05 15:06:11 +00:00
Code Activity

Test.

Browse source
This commit is contained in:
nella 2026-05-18 13:44:40 +02:00
parent bc07c6b1b0
commit 6c13ec0efb
5 changed files with 456 additions and 0 deletions
Download patch file Download diff file Expand all files Collapse all files

97
tests/arith_tree/arith_tree_final_adder.ys Normal file
View file

@ -0,0 +1,97 @@
read_verilog <<EOT
module final_auto_wide(
input [31:0] a, b, c, d,
output [31:0] y
);
assign y = a + b + c + d;
endmodule
EOT
hierarchy -auto-top
proc
equiv_opt arith_tree -final auto
design -load postopt
select -assert-count 1 t:$add
select -assert-count 2 t:$fa
select -assert-count 1 t:$add a:adder_arch=parallel_prefix %i
design -reset
read_verilog <<EOT
module final_auto_narrow(
input [7:0] a, b, c, d,
output [7:0] y
);
assign y = a + b + c + d;
endmodule
EOT
hierarchy -auto-top
proc
equiv_opt arith_tree -final auto
design -load postopt
select -assert-count 1 t:$add
select -assert-count 2 t:$fa
select -assert-count 0 t:$add a:adder_arch %i
design -reset
read_verilog <<EOT
module final_ripple(
input [31:0] a, b, c, d,
output [31:0] y
);
assign y = a + b + c + d;
endmodule
EOT
hierarchy -auto-top
proc
equiv_opt arith_tree -final ripple
design -load postopt
select -assert-count 1 t:$add
select -assert-count 0 t:$add a:adder_arch %i
design -reset
read_verilog <<EOT
module final_prefix_narrow(
input [7:0] a, b, c, d,
output [7:0] y
);
assign y = a + b + c + d;
endmodule
EOT
hierarchy -auto-top
proc
equiv_opt arith_tree -final prefix
design -load postopt
select -assert-count 1 t:$add a:adder_arch=parallel_prefix %i
design -reset
read_verilog <<EOT
module final_elarith(
input [15:0] a, b, c, d,
output [15:0] y
);
assign y = a + b + c + d;
endmodule
EOT
hierarchy -auto-top
proc
arith_tree -final elarith
select -assert-count 0 t:$add
select -assert-count 1 t:\AddCfast
select -assert-count 2 t:$fa
select -assert-count 2 t:$fa c:*emit_compressor_42* %i
design -reset
read_verilog <<EOT
module elarith_macro(
input [15:0] a, b, c, d,
output [15:0] y
);
assign y = a + b + c + d;
endmodule
EOT
hierarchy -auto-top
proc
arith_tree -elarith-macro
select -assert-count 0 t:$fa
select -assert-count 0 t:$add
select -assert-count 1 t:\AddMopCsv
design -reset