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Another block of spelling fixes
Smaller this time
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24 changed files with 53 additions and 53 deletions
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@ -27,14 +27,14 @@ module test04(a, y);
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assign y = ~(a - 1'b0);
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endmodule
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// .. this test triggers a bug in xilinx isim.
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// .. this test triggers a bug in Xilinx ISIM.
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// module test05(a, y);
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// input a;
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// output y;
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// assign y = 12345 >> {a, 32'd0};
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// endmodule
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// .. this test triggers a bug in icarus verilog.
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// .. this test triggers a bug in Icarus Verilog.
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// module test06(a, b, c, y);
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// input signed [3:0] a;
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// input signed [1:0] b;
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