mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-10-31 11:42:30 +00:00
Code Activity

Another block of spelling fixes

Browse source 
Smaller this time
This commit is contained in:
Larry Doolittle 2015-08-14 13:23:01 -07:00 • committed by Clifford Wolf
parent 022f570563
commit 6c00704a5e
24 changed files with 53 additions and 53 deletions
Download patch file Download diff file Expand all files Collapse all files

4
tests/simple/hierarchy.v
View file

@ -5,10 +5,10 @@ input [3:0] a;
input signed [3:0] b;
output [7:0] y1, y2, y3, y4;
// this version triggers a bug in icarus verilog
// this version triggers a bug in Icarus Verilog
// submod #(-3'sd1, 3'b111 + 3'b001) foo (a, b, y1, y2, y3, y4);
// this version is handled correctly by icarus verilog
// this version is handled correctly by Icarus Verilog
submod #(-3'sd1, -3'sd1) foo (a, b, y1, y2, y3, y4);
endmodule