mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-08-27 21:48:58 +00:00
Code Activity

Another block of spelling fixes

Browse source 
Smaller this time
This commit is contained in:
Larry Doolittle 2015-08-14 13:23:01 -07:00 • committed by Clifford Wolf
parent 022f570563
commit 6c00704a5e
24 changed files with 53 additions and 53 deletions
Download patch file Download diff file Expand all files Collapse all files

2
tests/simple/dff_different_styles.v
View file

@ -65,7 +65,7 @@ always @(posedge clk, posedge arst1, posedge arst2, negedge arst3) begin
end
endmodule
// SR-Flip-Flops are on the edge of well defined vewrilog constructs in terms of
// SR-Flip-Flops are on the edge of well defined Verilog constructs in terms of
// simulation-implementation mismatches. The following testcases try to cover the
// part that is defined and avoid the undefined cases.