Another block of spelling fixes

Smaller this time

tests/asicworld/README

@@ -1 +1 @@
-Borrowed verilog examples from http://www.asic-world.com/.
+Borrowed Verilog examples from http://www.asic-world.com/.

tests/hana/README

@@ -1,4 +1,4 @@
 
-This test cases are copied from the hana project:
+These test cases are copied from the hana project:
 https://sourceforge.net/projects/sim-sim/
 

tests/realmath/run-test.sh

@@ -15,7 +15,7 @@ for ((i = 0; i < 100; i++)); do
 	iverilog -o uut_${idx}_tb uut_${idx}_tb.v uut_${idx}.v uut_${idx}_syn.v
 	./uut_${idx}_tb | tee uut_${idx}.err
 	if test -s uut_${idx}.err; then
-		echo "Note: Make sure that 'iverilog' is an up-to-date git checkout of icarus verilog."
+		echo "Note: Make sure that 'iverilog' is an up-to-date git checkout of Icarus Verilog."
 		exit 1
 	fi
 	rm -f uut_${idx}.err

tests/simple/dff_different_styles.v

@@ -65,7 +65,7 @@ always @(posedge clk, posedge arst1, posedge arst2, negedge arst3) begin
 end
 endmodule
 
-// SR-Flip-Flops are on the edge of well defined vewrilog constructs in terms of
+// SR-Flip-Flops are on the edge of well defined Verilog constructs in terms of
 // simulation-implementation mismatches. The following testcases try to cover the
 // part that is defined and avoid the undefined cases.
 

tests/simple/hierarchy.v

@@ -5,10 +5,10 @@ input [3:0] a;
 input signed [3:0] b;
 output [7:0] y1, y2, y3, y4;
 
-// this version triggers a bug in icarus verilog
+// this version triggers a bug in Icarus Verilog
 // submod #(-3'sd1, 3'b111 + 3'b001) foo (a, b, y1, y2, y3, y4);
 
-// this version is handled correctly by icarus verilog
+// this version is handled correctly by Icarus Verilog
 submod #(-3'sd1, -3'sd1) foo (a, b, y1, y2, y3, y4);
 
 endmodule

tests/simple/rotate.v

@@ -1,5 +1,5 @@
 
-// test case taken from amber23 verilog code
+// test case taken from amber23 Verilog code
 module a23_barrel_shift_fpga_rotate(i_in, direction, shift_amount, rot_prod);
 
 input  [31:0] i_in;

tests/simple/vloghammer.v

@@ -27,14 +27,14 @@ module test04(a, y);
   assign y = ~(a - 1'b0);
 endmodule
 
-// .. this test triggers a bug in xilinx isim.
+// .. this test triggers a bug in Xilinx ISIM.
 // module test05(a, y);
 //   input a;
 //   output y;
 //   assign y = 12345 >> {a, 32'd0};
 // endmodule
 
-// .. this test triggers a bug in icarus verilog.
+// .. this test triggers a bug in Icarus Verilog.
 // module test06(a, b, c, y);
 //   input signed [3:0] a;
 //   input signed [1:0] b;

tests/tools/autotest.sh

@@ -168,7 +168,7 @@ do
 	else
 		echo "${status_prefix}-> ERROR!"
 		if $warn_iverilog_git; then
-			echo "Note: Make sure that 'iverilog' is an up-to-date git checkout of icarus verilog."
+			echo "Note: Make sure that 'iverilog' is an up-to-date git checkout of Icarus Verilog."
 		fi
 		$keeprunning || exit 1
 	fi