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Another block of spelling fixes

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Larry Doolittle 2015-08-14 13:23:01 -07:00 • committed by Clifford Wolf
parent 022f570563
commit 6c00704a5e
24 changed files with 53 additions and 53 deletions
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techlibs/common/techmap.v
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@ -19,7 +19,7 @@
*
* The internal logic cell technology mapper.
*
* This verilog library contains the mapping of internal cells (e.g. $not with
* This Verilog library contains the mapping of internal cells (e.g. $not with
* variable bit width) to the internal logic cells (such as the single bit $_NOT_
* gate). Usually this logic network is then mapped to the actual technology
* using e.g. the "abc" pass.