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Another block of spelling fixes

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Smaller this time
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Larry Doolittle 2015-08-14 13:23:01 -07:00 • committed by Clifford Wolf
parent 022f570563
commit 6c00704a5e
24 changed files with 53 additions and 53 deletions
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4
techlibs/common/simlib.v
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@ -19,7 +19,7 @@
*
* The Simulation Library.
*
* This verilog library contains simple simulation models for the internal
* This Verilog library contains simple simulation models for the internal
* cells ($not, ...) generated by the frontends and used in most passes.
*
* This library can be used to verify the internal netlists as generated
@ -1163,7 +1163,7 @@ input A, EN;
`ifndef SIMLIB_NOCHECKS
always @* begin
if (A !== 1'b1 && EN === 1'b1) begin
$display("Assertation %m failed!");
$display("Assertion %m failed!");
$stop;
end
end