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Another block of spelling fixes

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Larry Doolittle 2015-08-14 13:23:01 -07:00 • committed by Clifford Wolf
parent 022f570563
commit 6c00704a5e
24 changed files with 53 additions and 53 deletions
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techlibs/common/simcells.v
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@ -19,7 +19,7 @@
*
* The internal logic cell simulation library.
*
* This verilog library contains simple simulation models for the internal
* This Verilog library contains simple simulation models for the internal
* logic cells ($_NOT_ , $_AND_ , ...) that are generated by the default technology
* mapper (see "techmap.v" in this directory) and expected by the "abc" pass.
*