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Cleanup abc9.cc

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This commit is contained in:
Eddie Hung 2019-06-27 15:15:56 -07:00
parent fb30fcb7c5
commit 6bf73e3546
1 changed files with 17 additions and 15 deletions
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32
passes/techmap/abc9.cc
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@ -80,7 +80,7 @@ void handle_loops(RTLIL::Design *design)
{ {
Pass::call(design, "scc -set_attr abc_scc_id {}"); Pass::call(design, "scc -set_attr abc_scc_id {}");
dict<IdString, vector<IdString>> module_break; dict<IdString, vector<IdString>> abc_scc_break;
// For every unique SCC found, (arbitrarily) find the first // For every unique SCC found, (arbitrarily) find the first
// cell in the component, and select (and mark) all its output // cell in the component, and select (and mark) all its output
@ -116,12 +116,11 @@ void handle_loops(RTLIL::Design *design)
cell->attributes.erase(it); cell->attributes.erase(it);
} }
auto jt = module_break.find(cell->type); auto jt = abc_scc_break.find(cell->type);
if (jt == module_break.end()) { if (jt == abc_scc_break.end()) {
std::vector<IdString> ports; std::vector<IdString> ports;
if (!yosys_celltypes.cell_known(cell->type)) { RTLIL::Module* box_module = design->module(cell->type);
RTLIL::Module* box_module = design->module(cell->type); if (box_module) {
log_assert(box_module);
auto ports_csv = box_module->attributes.at("\\abc_scc_break", RTLIL::Const::from_string("")).decode_string(); auto ports_csv = box_module->attributes.at("\\abc_scc_break", RTLIL::Const::from_string("")).decode_string();
for (const auto &port_name : split_tokens(ports_csv, ",")) { for (const auto &port_name : split_tokens(ports_csv, ",")) {
auto port_id = RTLIL::escape_id(port_name); auto port_id = RTLIL::escape_id(port_name);
@ -131,7 +130,7 @@ void handle_loops(RTLIL::Design *design)
ports.push_back(port_id); ports.push_back(port_id);
} }
} }
jt = module_break.insert(std::make_pair(cell->type, std::move(ports))).first; jt = abc_scc_break.insert(std::make_pair(cell->type, std::move(ports))).first;
} }
for (auto port_name : jt->second) { for (auto port_name : jt->second) {
@ -554,17 +553,20 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
signal = std::move(bits); signal = std::move(bits);
} }
dict<IdString, bool> abc_box;
vector<RTLIL::Cell*> boxes; vector<RTLIL::Cell*> boxes;
for (auto it = module->cells_.begin(); it != module->cells_.end(); ) { for (auto cell : module->cells()) {
RTLIL::Cell* cell = it->second; if (cell->type.in("$_AND_", "$_NOT_")) {
if (cell->type.in("$_AND_", "$_NOT_", "$__ABC_FF_")) { module->remove(cell);
it = module->remove(it);
continue; continue;
} }
RTLIL::Module* box_module = design->module(cell->type); auto it = abc_box.find(cell->type);
if (box_module && box_module->attributes.count("\\abc_box_id")) if (it == abc_box.end()) {
boxes.emplace_back(it->second); RTLIL::Module* box_module = design->module(cell->type);
++it; it = abc_box.insert(std::make_pair(cell->type, box_module && box_module->attributes.count("\\abc_box_id"))).first;
}
if (it->second)
boxes.emplace_back(cell);
} }
std::map<std::string, int> cell_stats; std::map<std::string, int> cell_stats;