From 6bd2609f3485b649d8372615241f04783a39fb03 Mon Sep 17 00:00:00 2001 From: "Emil J. Tywoniak" Date: Fri, 7 Nov 2025 21:32:09 +0100 Subject: [PATCH] proc_dff: add wire src attributes to dff cells (cherry picked from commit 4072bcfd0ba711f0c44494c9328344c3a51347c7) --- passes/proc/proc_dff.cc | 25 +++++++++++++++++++++++++ tests/proc/proc_mux_src.ys | 7 ++----- 2 files changed, 27 insertions(+), 5 deletions(-) diff --git a/passes/proc/proc_dff.cc b/passes/proc/proc_dff.cc index d20567e18..52037dcd2 100644 --- a/passes/proc/proc_dff.cc +++ b/passes/proc/proc_dff.cc @@ -53,6 +53,25 @@ RTLIL::SigSpec find_any_lvalue(const RTLIL::Process *proc) return lvalue; } +void transfer_wire_sources(const SigSpec& sig, Cell* cell) +{ + std::vector refs; + pool seen; + TwineRef existing = cell->src_id(); + if (existing != Twine::Null) { + refs.push_back(existing); + seen.insert(existing); + } + for (auto chunk : sig.chunks()) + if (chunk.wire) { + TwineRef s = chunk.wire->src_id(); + if (s != Twine::Null && seen.insert(s).second) + refs.push_back(s); + } + if (!refs.empty()) + cell->set_src_attribute(cell->module->design->twines.concat(std::span{refs})); +} + void gen_dffsr_complex(RTLIL::Module *mod, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, RTLIL::SigSpec clk, bool clk_polarity, std::vector> &async_rules, RTLIL::Process *proc) { @@ -83,6 +102,8 @@ void gen_dffsr_complex(RTLIL::Module *mod, RTLIL::SigSpec sig_d, RTLIL::SigSpec RTLIL::Cell *cell = mod->addDffsr(Twine{sstr.str()}, clk, sig_sr_set, sig_sr_clr, sig_d, sig_q, clk_polarity); cell->attributes = proc->attributes; + transfer_wire_sources(sig_q, cell); + cell->module->design->merge_src(cell, proc); log(" created %s cell `%s' with %s edge clock and multiple level-sensitive resets.\n", log_id(cell->type), log_id(cell), clk_polarity ? "positive" : "negative"); @@ -96,6 +117,8 @@ void gen_aldff(RTLIL::Module *mod, RTLIL::SigSpec sig_in, RTLIL::SigSpec sig_set RTLIL::Cell *cell = mod->addCell(mod->design->twines.add(std::string{sstr.str()}), TW($aldff)); cell->attributes = proc->attributes; + transfer_wire_sources(sig_out, cell); + cell->module->design->merge_src(cell, proc); cell->parameters[ID::WIDTH] = RTLIL::Const(sig_in.size()); cell->parameters[ID::ALOAD_POLARITY] = RTLIL::Const(set_polarity, 1); @@ -118,6 +141,8 @@ void gen_dff(RTLIL::Module *mod, RTLIL::SigSpec sig_in, RTLIL::Const val_rst, RT RTLIL::Cell *cell = mod->addCell(mod->design->twines.add(std::string{sstr.str()}), clk.empty() ? TW($ff) : arst ? TW($adff) : TW($dff)); cell->attributes = proc->attributes; + transfer_wire_sources(sig_out, cell); + cell->module->design->merge_src(cell, proc); cell->parameters[ID::WIDTH] = RTLIL::Const(sig_in.size()); if (arst) { diff --git a/tests/proc/proc_mux_src.ys b/tests/proc/proc_mux_src.ys index e25858e26..8c146db70 100644 --- a/tests/proc/proc_mux_src.ys +++ b/tests/proc/proc_mux_src.ys @@ -5,9 +5,9 @@ check -assert select -assert-count 2 tiny2/t:$eq select -assert-count 1 tiny2/t:$eq a:src=proc_mux_src.v:81.4-81.10 %i select -assert-count 1 tiny2/t:$eq a:src=proc_mux_src.v:84.4-84.10 %i -# Flops cover the whole process +# Flops cover the assigned to wire and whole process select -assert-count 1 tiny2/t:$dff -select -assert-count 1 tiny2/t:$dff a:src=proc_mux_src.v:78.2-91.5 %i +select -assert-count 1 tiny2/t:$dff a:src=proc_mux_src.v:76.19-76.22|proc_mux_src.v:78.2-91.5 # Muxes are marked to the exact assignment statements they represent including the explicit default case select -assert-count 1 tiny2/t:$pmux select -assert-count 1 tiny2/t:$pmux a:src=proc_mux_src.v:80.5-80.13|proc_mux_src.v:83.5-83.15|proc_mux_src.v:86.5-86.15 @@ -18,8 +18,6 @@ select -assert-count 1 tiny/t:$mux select -assert-count 1 tiny/t:$mux a:proc_mux_src.v:65.5-65.13|proc_mux_src.v:63.3-67.10 select -assert-count 0 tiny/t:$reduce_or -dump nested -#dump nested/t:$pmux # $reduce_or src covers the entire list of comparison RHSs # Each snippet is treated separately so it gets its own $eq and $reduce_or etc select -assert-count 3 nested/t:$reduce_or @@ -30,4 +28,3 @@ select -assert-count 5 nested/t:$pmux select -assert-count 1 nested/t:$pmux a:src=proc_mux_src.v:21.5-21.20|proc_mux_src.v:26.5-26.20|proc_mux_src.v:32.5-45.12|proc_mux_src.v:48.5-48.19 %i # No nesting for output reg arith select -assert-count 1 nested/t:$pmux a:src=proc_mux_src.v:23.5-23.18|proc_mux_src.v:28.5-28.18|proc_mux_src.v:31.5-31.18|proc_mux_src.v:50.5-50.18 %i -dump nested/t:$pmux