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Don't blow up constants unneccessarily in Verilog frontend

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Clifford Wolf 2014-02-24 12:41:25 +01:00
parent dab1612f81
commit 6bc94b7eb2
1 changed files with 1 additions and 1 deletions
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frontends/ast/genrtlil.cc
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@ -906,7 +906,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
detectSignWidth(width_hint, sign_hint); detectSignWidth(width_hint, sign_hint);
is_signed = sign_hint; is_signed = sign_hint;
return RTLIL::SigSpec(bitsAsConst(width_hint, sign_hint)); return RTLIL::SigSpec(bitsAsConst());
} }
// simply return the corresponding RTLIL::SigSpec for an AST_IDENTIFIER node // simply return the corresponding RTLIL::SigSpec for an AST_IDENTIFIER node