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fixed edge cases in negopt passes, fixed cell naming inconsistencies

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This commit is contained in:
tondapusili 2026-02-06 16:38:55 -08:00
parent dc1847f89a
commit 6bb43f109c
17 changed files with 816 additions and 85 deletions
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81
tests/silimate/manual2sub.ys
View file

@ -21,6 +21,28 @@ select -assert-none t:$sub
design -reset
log -pop
log -header "Unsigned positive case"
log -push
design -reset
read_verilog <<EOF
module top(a, b, y);
input wire [7:0] a;
input wire [7:0] b;
output wire [7:0] y;
assign y = (a + ~b) + 1;
endmodule
EOF
proc; opt
check -assert
equiv_opt -assert negopt -pre
design -load postopt
select -assert-count 1 t:$add
select -assert-count 1 t:$neg
select -assert-none t:$not
select -assert-none t:$sub
design -reset
log -pop
log -header "Positive case B: 1 + (a + ~b) => a - b => a + (-b)"
log -push
design -reset
@ -44,6 +66,26 @@ select -assert-none t:$sub
design -reset
log -pop
log -header "Anchor case: output wider than operands"
log -push
design -reset
read_verilog <<EOF
module top(a, b, y);
input wire [7:0] a;
input wire [7:0] b;
output wire [11:0] y;
assign y = (a + ~b) + 1;
endmodule
EOF
proc; opt
check -assert
equiv_opt -assert negopt -pre
design -load postopt
select -assert-count 1 t:$neg
select -assert-none t:$sub
design -reset
log -pop
log -header "Negative case: fanout on inner add output"
log -push
design -reset
@ -71,3 +113,42 @@ select -assert-none t:$neg
design -reset
log -pop
log -header "Negative case: mixed signedness on inner add"
log -push
design -reset
read_verilog <<EOF
module top(a, b, y);
input wire signed [7:0] a;
input wire [7:0] b;
output wire signed [7:0] y;
assign y = (a + ~b) + 1;
endmodule
EOF
proc; opt
check -assert
equiv_opt -assert negopt -pre
design -load postopt
select -assert-none t:$sub
design -reset
log -pop
log -header "Negative case: ~b not directly on inner add input"
log -push
design -reset
read_verilog <<EOF
module top(a, b, y);
input wire [7:0] a;
input wire [7:0] b;
output wire [7:0] y;
wire [7:0] nb;
assign nb = ~b;
assign y = (a + (nb ^ 8'h00)) + 1;
endmodule
EOF
proc; opt
check -assert
equiv_opt -assert negopt -pre
design -load postopt
select -assert-none t:$sub
design -reset
log -pop

77
tests/silimate/muxneg.ys
View file

@ -42,3 +42,80 @@ select -assert-count 1 t:$mux
select -assert-count 1 t:$neg
design -reset
log -pop
log -header "Anchor case: neg branches narrower than mux output"
log -push
design -reset
read_verilog <<EOF
module top(a, b, s, y);
input wire signed [7:0] a;
input wire signed [7:0] b;
input wire s;
output wire signed [11:0] y;
wire signed [5:0] neg_a;
wire signed [7:0] neg_b;
assign neg_a = -a[5:0];
assign neg_b = -b[7:0];
assign y = s ? neg_a : neg_b;
endmodule
EOF
proc; opt
check -assert
equiv_opt -assert negopt -post
design -load postopt
select -assert-count 1 t:$mux
select -assert-count 2 t:$neg
design -reset
log -pop
log -header "Negative case: signedness mismatch on negations"
log -push
design -reset
read_verilog <<EOF
module top(a, b, s, y);
input wire signed [7:0] a;
input wire [7:0] b;
input wire s;
output wire signed [7:0] y;
(* keep *) wire signed [7:0] neg_a;
(* keep *) wire [7:0] neg_b;
assign neg_a = -a;
assign neg_b = -b;
assign y = s ? neg_a : neg_b;
endmodule
EOF
proc; opt
check -assert
equiv_opt -assert negopt -post
design -load postopt
select -assert-count 1 t:$mux
select -assert-count 2 t:$neg
design -reset
log -pop
log -header "Negative case: neg output has extra fanout"
log -push
design -reset
read_verilog <<EOF
module top(a, b, s, y, z);
input wire signed [7:0] a;
input wire signed [7:0] b;
input wire s;
output wire signed [7:0] y;
output wire signed [7:0] z;
(* keep *) wire signed [7:0] neg_a;
(* keep *) wire signed [7:0] neg_b;
assign neg_a = -a;
assign neg_b = -b;
assign y = s ? neg_a : neg_b;
assign z = neg_a;
endmodule
EOF
proc; opt
check -assert
equiv_opt -assert negopt -post
design -load postopt
select -assert-count 1 t:$mux
select -assert-count 2 t:$neg
design -reset
log -pop

96
tests/silimate/neg2sub.ys
View file

@ -5,7 +5,7 @@ read_verilog <<EOF
module top(a, b, y);
input wire signed [7:0] a;
input wire signed [7:0] b;
output wire signed [8:0] y;
output wire signed [7:0] y;
assign y = a + (-b);
endmodule
EOF
@ -26,7 +26,7 @@ read_verilog <<EOF
module top(a, b, y);
input wire signed [7:0] a;
input wire signed [7:0] b;
output wire signed [8:0] y;
output wire signed [7:0] y;
assign y = (-a) + b;
endmodule
EOF
@ -39,3 +39,95 @@ select -assert-none t:$add
select -assert-none t:$neg
design -reset
log -pop
log -header "Unsigned positive case"
log -push
design -reset
read_verilog <<EOF
module top(a, b, y);
input wire [7:0] a;
input wire [7:0] b;
output wire [7:0] y;
assign y = a + (-b);
endmodule
EOF
proc; opt
check -assert
equiv_opt -assert negopt -post
design -load postopt
select -assert-count 1 t:$sub
select -assert-none t:$add
select -assert-none t:$neg
design -reset
log -pop
log -header "Negative case: output wider than negation"
log -push
design -reset
read_verilog <<EOF
module top(a, b, y);
input wire signed [7:0] a;
input wire signed [7:0] b;
output wire signed [8:0] y;
wire signed [7:0] nb;
assign nb = -b;
assign y = a + nb;
endmodule
EOF
proc; opt
check -assert
equiv_opt -assert negopt -post
design -load postopt
select -assert-count 1 t:$add
select -assert-count 1 t:$neg
select -assert-none t:$sub
design -reset
log -pop
log -header "Negative case: negation truncates input"
log -push
design -reset
read_verilog <<EOF
module top(a, b, y);
input wire signed [7:0] a;
input wire signed [7:0] b;
output wire signed [3:0] y;
wire signed [3:0] nb;
assign nb = -b;
assign y = a[3:0] + nb;
endmodule
EOF
proc; opt
check -assert
equiv_opt -assert negopt -post
design -load postopt
select -assert-count 1 t:$add
select -assert-count 1 t:$neg
select -assert-none t:$sub
design -reset
log -pop
log -header "Negative case: neg output has extra fanout"
log -push
design -reset
read_verilog <<EOF
module top(a, b, y, z);
input wire signed [7:0] a;
input wire signed [7:0] b;
output wire signed [7:0] y;
output wire signed [7:0] z;
(* keep *) wire signed [7:0] nb;
assign nb = -b;
assign y = a + nb;
assign z = nb;
endmodule
EOF
proc; opt
check -assert
equiv_opt -assert negopt -post
design -load postopt
select -assert-count 1 t:$add
select -assert-count 1 t:$neg
select -assert-none t:$sub
design -reset
log -pop

60
tests/silimate/negexpand.ys
View file

@ -18,6 +18,26 @@ select -assert-count 2 t:$neg
design -reset
log -pop
log -header "Unsigned positive case"
log -push
design -reset
read_verilog <<EOF
module top(a, b, y);
input wire [7:0] a;
input wire [7:0] b;
output wire [7:0] y;
assign y = -(a + b);
endmodule
EOF
proc; opt
check -assert
equiv_opt -assert negopt -pre
design -load postopt
select -assert-count 1 t:$add
select -assert-count 2 t:$neg
design -reset
log -pop
log -header "Width extension case (output wider than inputs)"
log -push
design -reset
@ -39,6 +59,26 @@ select -assert-count 2 t:$neg
design -reset
log -pop
log -header "Anchor case: inputs narrower than neg output"
log -push
design -reset
read_verilog <<EOF
module top(a, b, y);
input wire signed [3:0] a;
input wire signed [3:0] b;
output wire signed [7:0] y;
assign y = -(a + b);
endmodule
EOF
proc; opt
check -assert
equiv_opt -assert negopt -pre
design -load postopt
select -assert-count 1 t:$add
select -assert-count 2 t:$neg
design -reset
log -pop
log -header "Negative case: fanout on add output"
log -push
design -reset
@ -63,3 +103,23 @@ select -assert-count 1 t:$add
select -assert-count 1 t:$neg
design -reset
log -pop
log -header "Coerced signedness case"
log -push
design -reset
read_verilog <<EOF
module top(a, b, y);
input wire signed [7:0] a;
input wire [7:0] b;
output wire signed [7:0] y;
assign y = -(a + b);
endmodule
EOF
proc; opt
check -assert
equiv_opt -assert negopt -pre
design -load postopt
select -assert-count 1 t:$add
select -assert-count 2 t:$neg
design -reset
log -pop

69
tests/silimate/negmux.ys
View file

@ -67,3 +67,72 @@ select -assert-count 1 t:$mux
select -assert-count 1 t:$neg
design -reset
log -pop
log -header "Anchor case: mux inputs narrower than neg output"
log -push
design -reset
read_verilog <<EOF
module top(a, b, s, y);
input wire signed [3:0] a;
input wire signed [3:0] b;
input wire s;
output wire signed [7:0] y;
wire signed [3:0] m;
assign m = s ? a : b;
assign y = -m;
endmodule
EOF
proc; opt
check -assert
equiv_opt -assert negopt -pre
design -load postopt
select -assert-count 1 t:$mux
select -assert-count 2 t:$neg
design -reset
log -pop
log -header "Negative case: signedness mismatch on mux output"
log -push
design -reset
read_verilog <<EOF
module top(a, b, s, y);
input wire signed [7:0] a;
input wire [7:0] b;
input wire s;
output wire signed [7:0] y;
wire [7:0] m;
assign m = s ? a : b;
assign y = -m;
endmodule
EOF
proc; opt
check -assert
equiv_opt -assert negopt -pre
design -load postopt
select -assert-count 1 t:$mux
select -assert-none t:$sub
design -reset
log -pop
log -header "Negative case: neg input not from mux output"
log -push
design -reset
read_verilog <<EOF
module top(a, b, s, y);
input wire signed [7:0] a;
input wire signed [7:0] b;
input wire s;
output wire signed [7:0] y;
wire signed [7:0] m;
assign m = s ? a : b;
assign y = -(m ^ 8'h00);
endmodule
EOF
proc; opt
check -assert
equiv_opt -assert negopt -pre
design -load postopt
select -assert-count 1 t:$mux
select -assert-none t:$sub
design -reset
log -pop

20
tests/silimate/negneg.ys
View file

@ -58,3 +58,23 @@ design -load postopt
select -assert-count 2 t:$neg
design -reset
log -pop
log -header "Anchor case: inner neg truncates"
log -push
design -reset
read_verilog <<EOF
module top(a, y);
input wire signed [7:0] a;
output wire signed [6:0] y;
wire signed [6:0] neg_a;
assign neg_a = -a;
assign y = -neg_a;
endmodule
EOF
proc; opt
check -assert
equiv_opt -assert negopt -pre
design -load postopt
select -assert-count 2 t:$neg
design -reset
log -pop

91
tests/silimate/negrebuild.ys
View file

@ -15,5 +15,96 @@ equiv_opt -assert negopt -post
design -load postopt
select -assert-count 1 t:$add
select -assert-count 1 t:$neg
select -assert-none t:$sub
design -reset
log -pop
log -header "Unsigned positive case"
log -push
design -reset
read_verilog <<EOF
module top(a, b, y);
input wire [7:0] a;
input wire [7:0] b;
output wire [7:0] y;
assign y = (-a) + (-b);
endmodule
EOF
proc; opt
check -assert
equiv_opt -assert negopt -post
design -load postopt
select -assert-count 1 t:$add
select -assert-count 1 t:$neg
select -assert-none t:$sub
design -reset
log -pop
log -header "Anchor case: neg branches with different widths"
log -push
design -reset
read_verilog <<EOF
module top(a, b, y);
input wire signed [7:0] a;
input wire signed [9:0] b;
output wire signed [11:0] y;
wire signed [5:0] n1;
wire signed [7:0] n2;
assign n1 = -a[5:0];
assign n2 = -b[7:0];
assign y = n1 + n2;
endmodule
EOF
proc; opt
check -assert
equiv_opt -assert negopt -post
design -load postopt
select -assert-count 1 t:$add
select -assert-none t:$sub
design -reset
log -pop
log -header "Negative case: signedness mismatch on negations"
log -push
design -reset
read_verilog <<EOF
module top(a, b, y);
input wire signed [7:0] a;
input wire [7:0] b;
output wire signed [7:0] y;
assign y = (-a) + (-b);
endmodule
EOF
proc; opt
check -assert
equiv_opt -assert negopt -post
design -load postopt
select -assert-count 1 t:$add
select -assert-none t:$sub
design -reset
log -pop
log -header "Negative case: add input not direct neg output"
log -push
design -reset
read_verilog <<EOF
module top(a, b, y);
input wire signed [7:0] a;
input wire signed [7:0] b;
output wire signed [7:0] y;
wire signed [7:0] na;
wire signed [7:0] nb;
assign na = -a;
assign nb = -b;
assign y = (na ^ 8'h00) + nb;
endmodule
EOF
proc; opt
check -assert
equiv_opt -assert negopt -post
design -load postopt
select -assert-count 1 t:$add
select -assert-count 2 t:$neg
select -assert-none t:$sub
design -reset
log -pop

65
tests/silimate/sub2neg.ys
View file

@ -9,6 +9,28 @@ module top(a, b, y);
assign y = a - b;
endmodule
EOF
proc; opt
check -assert
equiv_opt -assert negopt -pre
design -load postopt
select -assert-count 1 t:$add
select -assert-count 1 t:$neg
select -assert-none t:$sub
design -reset
log -pop
log -header "Unsigned positive case"
log -push
design -reset
read_verilog <<EOF
module top(a, b, y);
input wire [7:0] a;
input wire [7:0] b;
output wire [7:0] y;
assign y = a - b;
endmodule
EOF
proc; opt
check -assert
equiv_opt -assert negopt -pre
design -load postopt
@ -28,6 +50,7 @@ module top(a, y);
assign y = a - 8'd5;
endmodule
EOF
proc; opt
check -assert
equiv_opt -assert negopt -pre
design -load postopt
@ -37,3 +60,45 @@ select -assert-none t:$add
select -assert-none t:$neg
design -reset
log -pop
log -header "Anchor case: output wider than inputs"
log -push
design -reset
read_verilog <<EOF
module top(a, b, y);
input wire signed [7:0] a;
input wire signed [7:0] b;
output wire signed [11:0] y;
assign y = a - b;
endmodule
EOF
proc; opt
check -assert
equiv_opt -assert negopt -pre
design -load postopt
select -assert-count 1 t:$add
select -assert-count 1 t:$neg
select -assert-none t:$sub
design -reset
log -pop
log -header "Signedness case"
log -push
design -reset
read_verilog <<EOF
module top(a, b, y);
input wire signed [7:0] a;
input wire [7:0] b;
output wire signed [7:0] y;
assign y = a - b;
endmodule
EOF
proc; opt
check -assert
equiv_opt -assert negopt -pre
design -load postopt
select -assert-count 1 t:$add
select -assert-count 1 t:$neg
select -assert-none t:$sub
design -reset
log -pop