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Update abc9_xc7.box comments

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Eddie Hung 2019-12-31 15:25:46 -08:00
parent 4cdba00e25
commit 6b825c719b
1 changed files with 18 additions and 18 deletions
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34
techlibs/xilinx/abc9_xc7.box
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@ -1,8 +1,9 @@
# Max delays from https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLL_L.sdf
# https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf
# NB: Inputs/Outputs must be ordered alphabetically
# (with exceptions for carry in/out)
# NB: Box inputs/outputs must each be in the same order
# as their corresponding module definition
# (with exceptions detailed below)
# Average across F7[AB]MUX
# Inputs: I0 I1 S0
@ -15,7 +16,7 @@ MUXF7 1 1 3 1
MUXF8 2 1 3 1
104 94 273
# Box containing MUXF7.[AB] + MUXF8,
# Box containing MUXF7.[AB] + MUXF8
# Necessary to make these an atomic unit so that
# ABC cannot optimise just one of the MUXF7 away
# and expect to save on its delay
@ -27,8 +28,8 @@ $__MUXF78 3 1 6 1
# CARRY4 + CARRY4_[ABCD]X
# Inputs: CYINIT DI0 DI1 DI2 DI3 S0 S1 S2 S3 CI
# Outputs: O0 O1 O2 O3 CO0 CO1 CO2 CO3
# (NB: carry chain input/output must be last
# input/output and the entire bus has been
# (Exception: carry chain input/output must be the
# last input and output and the entire bus has been
# moved there overriding the otherwise
# alphabetical ordering)
CARRY4 4 1 10 8
@ -53,55 +54,54 @@ $__ABC9_ASYNC0 1000 1 2 1
$__ABC9_ASYNC1 1001 1 2 1
0 764
# Max delays from https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L237-L251
# Flop boxes:
# * Max delays from https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L237-L251
# https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L265-L277
# * Exception: $abc9_currQ is a special input (located last) necessary for clock-enable functionality
# NB: Inputs/Outputs must be ordered alphabetically
# (with exception for \$currQ)
# Inputs: C CE D R \$currQ
# Inputs: C CE D R $abc9_currQ
# Outputs: Q
FDRE 1100 1 5 1
#0 109 -46 404 0
0 109 0 404 0 # Clamp -46ps Tsu
# Inputs: C CE D R \$currQ
# Inputs: C CE D R $abc9_currQ
# Outputs: Q
FDRE_1 1101 1 5 1
#0 109 0 -46 404
0 109 0 0 404 # Clamp -46ps Tsu
# Inputs: C CE CLR D \$currQ
# Inputs: C CE CLR D $abc9_currQ
# Outputs: Q
FDCE 1102 1 5 1
#0 109 764 -46 0
0 109 764 0 0 # Clamp -46ps Tsu
# Inputs: C CE CLR D \$currQ
# Inputs: C CE CLR D $abc9_currQ
# Outputs: Q
FDCE_1 1103 1 5 1
#0 109 764 -46 0
0 109 764 0 0 # Clamp -46ps Tsu
# Inputs: C CE D PRE \$currQ
# Inputs: C CE D PRE $abc9_currQ
# Outputs: Q
FDPE 1104 1 5 1
#0 109 -46 764 0
0 109 0 764 0 # Clamp -46ps Tsu
# Inputs: C CE D PRE \$currQ
# Inputs: C CE D PRE $abc9_currQ
# Outputs: Q
FDPE_1 1105 1 5 1
#0 109 -46 764 0
0 109 0 764 0 # Clamp -46ps Tsu
# Inputs: C CE D S \$currQ
# Inputs: C CE D S $abc9_currQ
# Outputs: Q
FDSE 1106 1 5 1
#0 109 -46 446 0
0 109 0 446 0 # Clamp -46ps Tsu
# Inputs: C CE D S \$currQ
# Inputs: C CE D S $abc9_currQ
# Outputs: Q
FDSE_1 1107 1 5 1
#0 109 -46 446 0