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verilog: fix multiple AST_PREFIX scope resolution issues

- Root AST_PREFIX nodes are now subject to genblk expansion to allow
  them to refer to a locally-visible generate block
- Part selects on AST_PREFIX member leafs can now refer to generate
  block items (previously would not resolve and raise an error)
- Add source location information to AST_PREFIX nodes
This commit is contained in:
Zachary Snow 2021-08-02 18:42:34 -06:00 committed by Zachary Snow
parent 3931b3a03f
commit 6b7267b849
4 changed files with 110 additions and 4 deletions

95
tests/verilog/prefix.sv Normal file
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@ -0,0 +1,95 @@
module top;
genvar i, j;
if (1) begin : blk1
integer a = 1;
for (i = 0; i < 2; i = i + 1) begin : blk2
integer b = i;
for (j = 0; j < 2; j = j + 1) begin : blk3
integer c = j;
localparam x = i;
localparam y = j;
always @* begin
assert (1 == a);
assert (1 == blk1.a);
assert (1 == top.blk1.a);
assert (i == b);
assert (i == blk2[i].b);
assert (i == blk1.blk2[i].b);
assert (i == top.blk1.blk2[i].b);
assert (i == blk2[x].b);
assert (i == blk1.blk2[x].b);
assert (i == top.blk1.blk2[x].b);
assert (j == c);
assert (j == blk3[j].c);
assert (j == blk2[x].blk3[j].c);
assert (j == blk1.blk2[x].blk3[j].c);
assert (j == top.blk1.blk2[x].blk3[j].c);
assert (j == c);
assert (j == blk3[y].c);
assert (j == blk2[x].blk3[y].c);
assert (j == blk1.blk2[x].blk3[y].c);
assert (j == top.blk1.blk2[x].blk3[y].c);
assert (j == top.blk1.blk2[x].blk3[y].c[0]);
assert (0 == top.blk1.blk2[x].blk3[y].c[1]);
assert (0 == top.blk1.blk2[x].blk3[y].c[j]);
end
end
always @* begin
assert (1 == a);
assert (1 == blk1.a);
assert (1 == top.blk1.a);
assert (i == b);
assert (i == blk2[i].b);
assert (i == blk1.blk2[i].b);
assert (i == top.blk1.blk2[i].b);
assert (0 == blk3[0].c);
assert (0 == blk2[i].blk3[0].c);
assert (0 == blk1.blk2[i].blk3[0].c);
assert (0 == top.blk1.blk2[i].blk3[0].c);
assert (1 == blk3[1].c);
assert (1 == blk2[i].blk3[1].c);
assert (1 == blk1.blk2[i].blk3[1].c);
assert (1 == top.blk1.blk2[i].blk3[1].c);
end
end
always @* begin
assert (1 == a);
assert (1 == blk1.a);
assert (1 == top.blk1.a);
assert (0 == blk2[0].b);
assert (0 == blk1.blk2[0].b);
assert (0 == top.blk1.blk2[0].b);
assert (1 == blk2[1].b);
assert (1 == blk1.blk2[1].b);
assert (1 == top.blk1.blk2[1].b);
assert (0 == blk2[0].blk3[0].c);
assert (0 == blk1.blk2[0].blk3[0].c);
assert (0 == top.blk1.blk2[0].blk3[0].c);
assert (1 == blk2[0].blk3[1].c);
assert (1 == blk1.blk2[0].blk3[1].c);
assert (1 == top.blk1.blk2[0].blk3[1].c);
assert (0 == blk2[1].blk3[0].c);
assert (0 == blk1.blk2[1].blk3[0].c);
assert (0 == top.blk1.blk2[1].blk3[0].c);
assert (1 == blk2[1].blk3[1].c);
assert (1 == blk1.blk2[1].blk3[1].c);
assert (1 == top.blk1.blk2[1].blk3[1].c);
end
end
always @* begin
assert (1 == blk1.a);
assert (1 == top.blk1.a);
assert (0 == blk1.blk2[0].b);
assert (0 == top.blk1.blk2[0].b);
assert (1 == blk1.blk2[1].b);
assert (1 == top.blk1.blk2[1].b);
assert (0 == blk1.blk2[0].blk3[0].c);
assert (0 == top.blk1.blk2[0].blk3[0].c);
assert (1 == blk1.blk2[0].blk3[1].c);
assert (1 == top.blk1.blk2[0].blk3[1].c);
assert (0 == blk1.blk2[1].blk3[0].c);
assert (0 == top.blk1.blk2[1].blk3[0].c);
assert (1 == blk1.blk2[1].blk3[1].c);
assert (1 == top.blk1.blk2[1].blk3[1].c);
end
endmodule

5
tests/verilog/prefix.ys Normal file
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read_verilog -sv prefix.sv
hierarchy
proc
select -module top
sat -verify -seq 1 -prove-asserts -show-all