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verilog: fix multiple AST_PREFIX scope resolution issues
- Root AST_PREFIX nodes are now subject to genblk expansion to allow them to refer to a locally-visible generate block - Part selects on AST_PREFIX member leafs can now refer to generate block items (previously would not resolve and raise an error) - Add source location information to AST_PREFIX nodes
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4 changed files with 110 additions and 4 deletions
95
tests/verilog/prefix.sv
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95
tests/verilog/prefix.sv
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module top;
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genvar i, j;
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if (1) begin : blk1
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integer a = 1;
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for (i = 0; i < 2; i = i + 1) begin : blk2
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integer b = i;
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for (j = 0; j < 2; j = j + 1) begin : blk3
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integer c = j;
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localparam x = i;
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localparam y = j;
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always @* begin
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assert (1 == a);
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assert (1 == blk1.a);
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assert (1 == top.blk1.a);
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assert (i == b);
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assert (i == blk2[i].b);
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assert (i == blk1.blk2[i].b);
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assert (i == top.blk1.blk2[i].b);
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assert (i == blk2[x].b);
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assert (i == blk1.blk2[x].b);
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assert (i == top.blk1.blk2[x].b);
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assert (j == c);
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assert (j == blk3[j].c);
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assert (j == blk2[x].blk3[j].c);
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assert (j == blk1.blk2[x].blk3[j].c);
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assert (j == top.blk1.blk2[x].blk3[j].c);
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assert (j == c);
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assert (j == blk3[y].c);
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assert (j == blk2[x].blk3[y].c);
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assert (j == blk1.blk2[x].blk3[y].c);
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assert (j == top.blk1.blk2[x].blk3[y].c);
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assert (j == top.blk1.blk2[x].blk3[y].c[0]);
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assert (0 == top.blk1.blk2[x].blk3[y].c[1]);
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assert (0 == top.blk1.blk2[x].blk3[y].c[j]);
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end
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end
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always @* begin
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assert (1 == a);
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assert (1 == blk1.a);
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assert (1 == top.blk1.a);
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assert (i == b);
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assert (i == blk2[i].b);
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assert (i == blk1.blk2[i].b);
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assert (i == top.blk1.blk2[i].b);
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assert (0 == blk3[0].c);
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assert (0 == blk2[i].blk3[0].c);
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assert (0 == blk1.blk2[i].blk3[0].c);
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assert (0 == top.blk1.blk2[i].blk3[0].c);
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assert (1 == blk3[1].c);
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assert (1 == blk2[i].blk3[1].c);
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assert (1 == blk1.blk2[i].blk3[1].c);
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assert (1 == top.blk1.blk2[i].blk3[1].c);
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end
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end
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always @* begin
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assert (1 == a);
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assert (1 == blk1.a);
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assert (1 == top.blk1.a);
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assert (0 == blk2[0].b);
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assert (0 == blk1.blk2[0].b);
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assert (0 == top.blk1.blk2[0].b);
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assert (1 == blk2[1].b);
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assert (1 == blk1.blk2[1].b);
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assert (1 == top.blk1.blk2[1].b);
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assert (0 == blk2[0].blk3[0].c);
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assert (0 == blk1.blk2[0].blk3[0].c);
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assert (0 == top.blk1.blk2[0].blk3[0].c);
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assert (1 == blk2[0].blk3[1].c);
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assert (1 == blk1.blk2[0].blk3[1].c);
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assert (1 == top.blk1.blk2[0].blk3[1].c);
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assert (0 == blk2[1].blk3[0].c);
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assert (0 == blk1.blk2[1].blk3[0].c);
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assert (0 == top.blk1.blk2[1].blk3[0].c);
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assert (1 == blk2[1].blk3[1].c);
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assert (1 == blk1.blk2[1].blk3[1].c);
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assert (1 == top.blk1.blk2[1].blk3[1].c);
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end
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end
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always @* begin
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assert (1 == blk1.a);
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assert (1 == top.blk1.a);
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assert (0 == blk1.blk2[0].b);
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assert (0 == top.blk1.blk2[0].b);
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assert (1 == blk1.blk2[1].b);
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assert (1 == top.blk1.blk2[1].b);
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assert (0 == blk1.blk2[0].blk3[0].c);
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assert (0 == top.blk1.blk2[0].blk3[0].c);
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assert (1 == blk1.blk2[0].blk3[1].c);
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assert (1 == top.blk1.blk2[0].blk3[1].c);
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assert (0 == blk1.blk2[1].blk3[0].c);
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assert (0 == top.blk1.blk2[1].blk3[0].c);
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assert (1 == blk1.blk2[1].blk3[1].c);
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assert (1 == top.blk1.blk2[1].blk3[1].c);
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end
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endmodule
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5
tests/verilog/prefix.ys
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5
tests/verilog/prefix.ys
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@ -0,0 +1,5 @@
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read_verilog -sv prefix.sv
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hierarchy
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proc
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select -module top
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sat -verify -seq 1 -prove-asserts -show-all
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