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sim: Evaluate all cells once
If a cell starts with undefined inputs and the value of those inputs is never changed, `sim` code will never evaluate that cell. This means its output will be left at undefined, but in some edge cases such cell can evaluate to a defined value. To address those cases evaluate all cells at least once.
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1 changed files with 13 additions and 9 deletions
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@ -287,16 +287,18 @@ struct SimInstance
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if (mod != nullptr) {
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if (mod != nullptr) {
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dirty_children.insert(new SimInstance(shared, scope + "." + RTLIL::unescape_id(cell->name), mod, cell, this));
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dirty_children.insert(new SimInstance(shared, scope + "." + RTLIL::unescape_id(cell->name), mod, cell, this));
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}
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} else {
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for (auto &port : cell->connections())
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for (auto &port : cell->connections()) {
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if (cell->input(port.first))
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if (cell->input(port.first))
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for (auto bit : sigmap(port.second)) {
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for (auto bit : sigmap(port.second))
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upd_cells[bit].insert(cell);
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upd_cells[bit].insert(cell);
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// Make sure cell inputs connected to constants are updated in the first cycle
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if (bit.wire == nullptr)
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// Update all cells in the first cycle (to propagate constants but also to
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dirty_bits.insert(bit);
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// handle edge cases in which cells have defined output values in presence of
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}
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// undefined inputs). This is with the exception of few cells which don't have
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// any inputs and should never be queued up for updating.
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if (!cell->type.in(ID($initstate), ID($anyconst), ID($anyseq), ID($allconst), ID($allseq)))
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dirty_cells.insert(cell);
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}
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}
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if (RTLIL::builtin_ff_cell_types().count(cell->type) || cell->type == ID($anyinit)) {
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if (RTLIL::builtin_ff_cell_types().count(cell->type) || cell->type == ID($anyinit)) {
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@ -492,6 +494,8 @@ struct SimInstance
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void update_cell(Cell *cell)
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void update_cell(Cell *cell)
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{
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{
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log_assert(!cell->type.in(ID($initstate), ID($anyconst), ID($anyseq), ID($allconst), ID($allseq)));
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if (ff_database.count(cell))
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if (ff_database.count(cell))
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return;
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return;
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