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opt_expr: requsted changes
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parent
83b095ab6c
commit
6b5507139e
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@ -1695,33 +1695,28 @@ skip_identity:
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SigSpec sig_y = assign_map(cell->getPort(ID::Y));
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int y_size = GetSize(sig_y);
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unsigned int bits = unsigned(sig_a.as_int());
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int bit_count = 0;
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for (; bits; bits >>= 1)
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bit_count += (bits & 1);
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int bit_idx;
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const auto onehot = sig_a.is_onehot(&bit_idx);
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if (bit_count == 1) {
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if (sig_a.as_int() == 2) {
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if (onehot) {
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if (bit_idx == 1) {
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log_debug("Replacing pow cell `%s' in module `%s' with left-shift\n",
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cell->name.c_str(), module->name.c_str());
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cell->type = ID($shl);
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cell->parameters[ID::A_WIDTH] = 1;
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cell->setPort(ID::A, Const(1, 1));
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cell->setPort(ID::A, Const(State::S1, 1));
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}
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else {
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log_debug("Replacing pow cell `%s' in module `%s' with multiply and left-shift\n",
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cell->name.c_str(), module->name.c_str());
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cell->type = ID($mul);
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cell->parameters[ID::A_SIGNED] = 0;
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int left_shift;
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sig_a.is_onehot(&left_shift);
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cell->setPort(ID::A, Const(left_shift, cell->parameters[ID::A_WIDTH].as_int()));
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cell->setPort(ID::A, Const(bit_idx, cell->parameters[ID::A_WIDTH].as_int()));
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SigSpec y_wire = module->addWire(NEW_ID, y_size);
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cell->setPort(ID::Y, y_wire);
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module->addShl(NEW_ID, Const(1, 1), y_wire, sig_y);
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module->addShl(NEW_ID, Const(State::S1, 1), y_wire, sig_y);
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}
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did_something = true;
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goto next_cell;
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