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dfflegalize: Add tests.
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37
tests/techmap/dfflegalize_dlatchsr.ys
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37
tests/techmap/dfflegalize_dlatchsr.ys
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read_verilog -icells <<EOT
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module dlatchsr(input E, R, S, D, output [3:0] Q);
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$_DLATCHSR_PPP_ ff0 (.E(E), .R(R), .S(S), .D(D), .Q(Q[0]));
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$_DLATCHSR_PPN_ ff1 (.E(E), .R(R), .S(S), .D(D), .Q(Q[1]));
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$_DLATCHSR_PNP_ ff2 (.E(E), .R(R), .S(S), .D(D), .Q(Q[2]));
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$_DLATCHSR_NPP_ ff3 (.E(E), .R(R), .S(S), .D(D), .Q(Q[3]));
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endmodule
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EOT
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design -save orig
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#equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DLATCH_PP0_ x -cell $_SR_PP_ x
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equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DLATCHSR_PPP_ x
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# Convert everything to ADLATCHs.
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design -load orig
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dfflegalize -cell $_DLATCH_PP0_ x -cell $_SR_PP_ x
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select -assert-count 14 t:$_NOT_
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select -assert-count 4 t:$_MUX_
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select -assert-count 8 t:$_DLATCH_PP0_
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select -assert-count 4 t:$_SR_PP_
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select -assert-none t:$_DLATCH_PP0_ t:$_SR_PP_ t:$_MUX_ t:$_NOT_ %% %n t:* %i
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# Convert everything to DLATCHSRs.
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design -load orig
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dfflegalize -cell $_DLATCHSR_PPP_ x
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select -assert-count 3 t:$_NOT_
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select -assert-count 0 t:$_MUX_
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select -assert-count 4 t:$_DLATCHSR_PPP_
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select -assert-none t:$_DLATCHSR_PPP_ t:$_MUX_ t:$_NOT_ %% %n t:* %i
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