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Wrap SB_CARRY+SB_LUT into $__ICE40_FULL_ADDER

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This commit is contained in:
Eddie Hung 2019-08-07 14:50:59 -07:00
parent 3414ee1e3f
commit 6b314c8371
3 changed files with 14 additions and 39 deletions
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22
techlibs/ice40/arith_map.v
View file

@ -44,7 +44,6 @@ module _80_ice40_alu (A, B, CI, BI, X, Y, CO);
genvar i; genvar i;
generate for (i = 0; i < Y_WIDTH; i = i + 1) begin:slice generate for (i = 0; i < Y_WIDTH; i = i + 1) begin:slice
`ifdef _ABC
\$__ICE40_FULL_ADDER carry ( \$__ICE40_FULL_ADDER carry (
.A(AA[i]), .A(AA[i]),
.B(BB[i]), .B(BB[i]),
@ -52,27 +51,6 @@ module _80_ice40_alu (A, B, CI, BI, X, Y, CO);
.CO(CO[i]), .CO(CO[i]),
.O(Y[i]) .O(Y[i])
); );
`else
SB_CARRY carry (
.I0(AA[i]),
.I1(BB[i]),
.CI(C[i]),
.CO(CO[i])
);
SB_LUT4 #(
// I0: 1010 1010 1010 1010
// I1: 1100 1100 1100 1100
// I2: 1111 0000 1111 0000
// I3: 1111 1111 0000 0000
.LUT_INIT(16'b 0110_1001_1001_0110)
) adder (
.I0(1'b0),
.I1(AA[i]),
.I2(BB[i]),
.I3(C[i]),
.O(Y[i])
);
`endif
end endgenerate end endgenerate
assign X = AA ^ BB; assign X = AA ^ BB;

22
techlibs/ice40/cells_map.v
View file

@ -62,7 +62,7 @@ module \$lut (A, Y);
endmodule endmodule
`endif `endif
`ifdef _ABC `ifndef NO_ADDER
module \$__ICE40_FULL_ADDER (output CO, O, input A, B, CI); module \$__ICE40_FULL_ADDER (output CO, O, input A, B, CI);
SB_CARRY carry ( SB_CARRY carry (
.I0(A), .I0(A),
@ -70,18 +70,16 @@ module \$__ICE40_FULL_ADDER (output CO, O, input A, B, CI);
.CI(CI), .CI(CI),
.CO(CO) .CO(CO)
); );
SB_LUT4 #( \$lut #(
// I0: 1010 1010 1010 1010 .WIDTH(4),
// I1: 1100 1100 1100 1100 // A[0]: 1010 1010 1010 1010
// I2: 1111 0000 1111 0000 // A[1]: 1100 1100 1100 1100
// I3: 1111 1111 0000 0000 // A[2]: 1111 0000 1111 0000
.LUT_INIT(16'b 0110_1001_1001_0110) // A[3]: 1111 1111 0000 0000
.LUT(16'b 0110_1001_1001_0110)
) adder ( ) adder (
.I0(1'b0), .A({CI,B,A,1'b0}),
.I1(A), .Y(O)
.I2(B),
.I3(CI),
.O(O)
); );
endmodule endmodule
`endif `endif

9
techlibs/ice40/synth_ice40.cc
View file

@ -238,7 +238,7 @@ struct SynthIce40Pass : public ScriptPass
{ {
if (check_label("begin")) if (check_label("begin"))
{ {
run("read_verilog -icells -lib -D_ABC +/ice40/cells_sim.v"); run("read_verilog -icells -lib +/ice40/cells_sim.v");
run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str())); run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str()));
run("proc"); run("proc");
} }
@ -294,7 +294,7 @@ struct SynthIce40Pass : public ScriptPass
if (nocarry) if (nocarry)
run("techmap"); run("techmap");
else else
run("techmap -map +/techmap.v -map +/ice40/arith_map.v" + std::string(abc == "abc9" ? " -D _ABC" : "")); run("techmap -map +/techmap.v -map +/ice40/arith_map.v");
if (retime || help_mode) if (retime || help_mode)
run(abc + " -dff", "(only if -retime)"); run(abc + " -dff", "(only if -retime)");
run("ice40_opt"); run("ice40_opt");
@ -309,7 +309,7 @@ struct SynthIce40Pass : public ScriptPass
run("opt_merge"); run("opt_merge");
run(stringf("dff2dffe -unmap-mince %d", min_ce_use)); run(stringf("dff2dffe -unmap-mince %d", min_ce_use));
} }
run("techmap -D NO_LUT -map +/ice40/cells_map.v"); run("techmap -D NO_LUT -D NO_ADDER -map +/ice40/cells_map.v");
run("opt_expr -mux_undef"); run("opt_expr -mux_undef");
run("simplemap"); run("simplemap");
run("ice40_ffinit"); run("ice40_ffinit");
@ -338,13 +338,12 @@ struct SynthIce40Pass : public ScriptPass
else else
wire_delay = 250; wire_delay = 250;
run(abc + stringf(" -W %d -lut +/ice40/abc_%s.lut -box +/ice40/abc_%s.box", wire_delay, device_opt.c_str(), device_opt.c_str()), "(skip if -noabc)"); run(abc + stringf(" -W %d -lut +/ice40/abc_%s.lut -box +/ice40/abc_%s.box", wire_delay, device_opt.c_str(), device_opt.c_str()), "(skip if -noabc)");
run("techmap -D NO_LUT -D _ABC -map +/ice40/cells_map.v");
} }
else else
run(abc + " -dress -lut 4", "(skip if -noabc)"); run(abc + " -dress -lut 4", "(skip if -noabc)");
} }
run("techmap -D NO_LUT -map +/ice40/cells_map.v");
run("clean"); run("clean");
run("ice40_unlut");
run("opt_lut -dlogic SB_CARRY:I0=2:I1=1:CI=0"); run("opt_lut -dlogic SB_CARRY:I0=2:I1=1:CI=0");
} }