mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-10-07 08:21:57 +00:00
Code Activity

Wrap SB_CARRY+SB_LUT into $__ICE40_FULL_ADDER

Browse source
This commit is contained in:
Eddie Hung 2019-08-07 14:50:59 -07:00
parent 3414ee1e3f
commit 6b314c8371
3 changed files with 14 additions and 39 deletions
Download patch file Download diff file Expand all files Collapse all files

9
techlibs/ice40/synth_ice40.cc
View file

@ -238,7 +238,7 @@ struct SynthIce40Pass : public ScriptPass
{
if (check_label("begin"))
{
run("read_verilog -icells -lib -D_ABC +/ice40/cells_sim.v");
run("read_verilog -icells -lib +/ice40/cells_sim.v");
run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str()));
run("proc");
}
@ -294,7 +294,7 @@ struct SynthIce40Pass : public ScriptPass
if (nocarry)
run("techmap");
else
run("techmap -map +/techmap.v -map +/ice40/arith_map.v" + std::string(abc == "abc9" ? " -D _ABC" : ""));
run("techmap -map +/techmap.v -map +/ice40/arith_map.v");
if (retime || help_mode)
run(abc + " -dff", "(only if -retime)");
run("ice40_opt");
@ -309,7 +309,7 @@ struct SynthIce40Pass : public ScriptPass
run("opt_merge");
run(stringf("dff2dffe -unmap-mince %d", min_ce_use));
}
run("techmap -D NO_LUT -map +/ice40/cells_map.v");
run("techmap -D NO_LUT -D NO_ADDER -map +/ice40/cells_map.v");
run("opt_expr -mux_undef");
run("simplemap");
run("ice40_ffinit");
@ -338,13 +338,12 @@ struct SynthIce40Pass : public ScriptPass
else
wire_delay = 250;
run(abc + stringf(" -W %d -lut +/ice40/abc_%s.lut -box +/ice40/abc_%s.box", wire_delay, device_opt.c_str(), device_opt.c_str()), "(skip if -noabc)");
run("techmap -D NO_LUT -D _ABC -map +/ice40/cells_map.v");
}
else
run(abc + " -dress -lut 4", "(skip if -noabc)");
}
run("techmap -D NO_LUT -map +/ice40/cells_map.v");
run("clean");
run("ice40_unlut");
run("opt_lut -dlogic SB_CARRY:I0=2:I1=1:CI=0");
}