mirror of
https://github.com/YosysHQ/yosys
synced 2025-09-05 17:47:44 +00:00
Wrap SB_CARRY+SB_LUT into $__ICE40_FULL_ADDER
This commit is contained in:
parent
3414ee1e3f
commit
6b314c8371
3 changed files with 14 additions and 39 deletions
|
@ -44,7 +44,6 @@ module _80_ice40_alu (A, B, CI, BI, X, Y, CO);
|
|||
|
||||
genvar i;
|
||||
generate for (i = 0; i < Y_WIDTH; i = i + 1) begin:slice
|
||||
`ifdef _ABC
|
||||
\$__ICE40_FULL_ADDER carry (
|
||||
.A(AA[i]),
|
||||
.B(BB[i]),
|
||||
|
@ -52,27 +51,6 @@ module _80_ice40_alu (A, B, CI, BI, X, Y, CO);
|
|||
.CO(CO[i]),
|
||||
.O(Y[i])
|
||||
);
|
||||
`else
|
||||
SB_CARRY carry (
|
||||
.I0(AA[i]),
|
||||
.I1(BB[i]),
|
||||
.CI(C[i]),
|
||||
.CO(CO[i])
|
||||
);
|
||||
SB_LUT4 #(
|
||||
// I0: 1010 1010 1010 1010
|
||||
// I1: 1100 1100 1100 1100
|
||||
// I2: 1111 0000 1111 0000
|
||||
// I3: 1111 1111 0000 0000
|
||||
.LUT_INIT(16'b 0110_1001_1001_0110)
|
||||
) adder (
|
||||
.I0(1'b0),
|
||||
.I1(AA[i]),
|
||||
.I2(BB[i]),
|
||||
.I3(C[i]),
|
||||
.O(Y[i])
|
||||
);
|
||||
`endif
|
||||
end endgenerate
|
||||
|
||||
assign X = AA ^ BB;
|
||||
|
|
Loading…
Add table
Add a link
Reference in a new issue