mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2026-05-25 19:36:21 +00:00
Code Activity

patch: wires

Browse source
This commit is contained in:
Emil J. Tywoniak 2026-05-19 15:33:41 +02:00
parent d2ae9b48e4
commit 6b16a0cac8
1 changed files with 26 additions and 4 deletions
Download patch file Download diff file Expand all files Collapse all files

30
kernel/unstable/patch.cc
View file

@ -27,13 +27,35 @@ Cell* Patch::addCell(IdString name, IdString type) {
}
Wire* Patch::addWire(IdString name, int width) {
(void)name;
(void)width;
log_assert(false);
return nullptr;
wires_.push_back(std::make_unique<Wire>(Wire::ConstructToken{}));
Wire* wire = wires_.back().get();
wire->name = name;
wire->width = width;
return wire;
}
// TODO code golf
RTLIL::Wire *RTLIL::Patch::addWire(RTLIL::IdString name, const RTLIL::Wire *other)
{
RTLIL::Wire *wire = addWire(std::move(name));
wire->width = other->width;
wire->start_offset = other->start_offset;
wire->port_id = other->port_id;
wire->port_input = other->port_input;
wire->port_output = other->port_output;
wire->upto = other->upto;
wire->is_signed = other->is_signed;
wire->attributes = other->attributes;
return wire;
}
void Patch::patch(Cell* old_cell, Cell* new_cell) {
for (auto& wire: wires_) {
Wire* raw = wire.release();
mod->wires_[raw->name] = raw;
}
pool<Cell*> patch_cells;
for (auto& cell: cells_) {
patch_cells.insert(cell.get());