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Add chain tests and tighten synthesis assertions for csa.

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nella 2026-03-13 13:14:32 +01:00 committed by nella
parent 335cce4895
commit 6b0caedcdd
21 changed files with 230 additions and 16 deletions

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@ -1,4 +1,5 @@
# Test bit correctness
read_verilog equiv_narrow.v
hierarchy -top equiv_add3
proc; opt_clean