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shim: init
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@ -2535,9 +2535,9 @@ RTLIL::Process *RTLIL::Module::addProcess(RTLIL::IdString name, const RTLIL::Pro
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add ## _func(name, sig_a, sig_y, is_signed, src); \
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return sig_y; \
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}
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DEF_METHOD(Not, sig_a.size(), ID($not))
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DEF_METHOD(Pos, sig_a.size(), ID($pos))
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DEF_METHOD(Neg, sig_a.size(), ID($neg))
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// DEF_METHOD(Not, sig_a.size(), ID($not))
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// DEF_METHOD(Pos, sig_a.size(), ID($pos))
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// DEF_METHOD(Neg, sig_a.size(), ID($neg))
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DEF_METHOD(ReduceAnd, 1, ID($reduce_and))
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DEF_METHOD(ReduceOr, 1, ID($reduce_or))
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DEF_METHOD(ReduceXor, 1, ID($reduce_xor))
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@ -1285,9 +1285,7 @@ public:
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// The add* methods create a cell and return the created cell. All signals must exist in advance.
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RTLIL::Cell* addNot (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = "");
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RTLIL::Cell* addPos (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = "");
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RTLIL::Cell* addNeg (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = "");
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#include "kernel/adds.shim.h"
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RTLIL::Cell* addAnd (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = "");
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RTLIL::Cell* addOr (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = "");
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