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Replaced more old SigChunk programming patterns

This commit is contained in:
Clifford Wolf 2014-07-24 22:47:57 +02:00
parent 7a608437c6
commit 6aa792c864
17 changed files with 101 additions and 104 deletions

View file

@ -35,10 +35,8 @@ struct BitPatternPool
if (width > 0) {
std::vector<RTLIL::State> pattern(width);
for (int i = 0; i < width; i++) {
RTLIL::SigSpec s = sig.extract(i, 1);
assert(s.chunks().size() == 1);
if (s.chunks()[0].wire == NULL && s.chunks()[0].data.bits[0] <= RTLIL::State::S1)
pattern[i] = s.chunks()[0].data.bits[0];
if (sig[i].wire == NULL && sig[i].data <= RTLIL::State::S1)
pattern[i] = sig[i].data;
else
pattern[i] = RTLIL::State::Sa;
}
@ -59,9 +57,7 @@ struct BitPatternPool
bits_t sig2bits(RTLIL::SigSpec sig)
{
assert(sig.is_fully_const());
assert(sig.chunks().size() == 1);
bits_t bits = sig.chunks()[0].data.bits;
bits_t bits = sig.as_const().bits;
for (auto &b : bits)
if (b > RTLIL::State::S1)
b = RTLIL::State::Sa;