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Replaced more old SigChunk programming patterns

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This commit is contained in:
Clifford Wolf 2014-07-24 22:47:57 +02:00
parent 7a608437c6
commit 6aa792c864
17 changed files with 101 additions and 104 deletions
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15
backends/edif/edif.cc
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@ -314,12 +314,9 @@ struct EdifBackend : public Backend {
}
}
for (auto &it : net_join_db) {
RTLIL::SigSpec sig = it.first;
log_assert(sig.size() == 1);
if (sig.chunks().at(0).wire == NULL) {
if (sig.chunks().at(0).data.bits.at(0) != RTLIL::State::S0 && sig.chunks().at(0).data.bits.at(0) != RTLIL::State::S1)
continue;
}
RTLIL::SigBit sig = it.first;
if (sig.wire == NULL && sig != RTLIL::State::S0 && sig != RTLIL::State::S1)
continue;
std::string netname = log_signal(sig);
for (size_t i = 0; i < netname.size(); i++)
if (netname[i] == ' ' || netname[i] == '\\')
@ -327,10 +324,10 @@ struct EdifBackend : public Backend {
fprintf(f, " (net %s (joined\n", EDIF_DEF(netname));
for (auto &ref : it.second)
fprintf(f, " %s\n", ref.c_str());
if (sig.chunks().at(0).wire == NULL) {
if (sig.chunks().at(0).data.bits.at(0) == RTLIL::State::S0)
if (sig.wire == NULL) {
if (sig == RTLIL::State::S0)
fprintf(f, " (portRef G (instanceRef GND))\n");
if (sig.chunks().at(0).data.bits.at(0) == RTLIL::State::S1)
if (sig == RTLIL::State::S1)
fprintf(f, " (portRef P (instanceRef VCC))\n");
}
fprintf(f, " ))\n");