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Replaced more old SigChunk programming patterns

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This commit is contained in:
Clifford Wolf 2014-07-24 22:47:57 +02:00
parent 7a608437c6
commit 6aa792c864
17 changed files with 101 additions and 104 deletions
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5
backends/autotest/autotest.cc
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@ -119,10 +119,9 @@ static void autotest(FILE *f, RTLIL::Design *design)
if ((*it4)->type == RTLIL::ST0 || (*it4)->type == RTLIL::ST1)
continue;
RTLIL::SigSpec &signal = (*it4)->signal;
for (size_t i = 0; i < signal.chunks().size(); i++) {
if (signal.chunks()[i].wire == wire)
for (auto &c : signal.chunks())
if (c.wire == wire)
is_clksignal = true;
}
}
if (is_clksignal && wire->attributes.count("\\gentb_constant") == 0) {
signal_clk[idy("sig", mod->name, wire->name)] = wire->width;