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cellmatch: Delegate evaluation to ConstEval

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Martin Povišer 2024-04-13 16:56:36 +02:00 • committed by Emil J. Tywoniak
parent 86e1080f05
commit 6a9858cdad
1 changed files with 28 additions and 75 deletions
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103
passes/techmap/cellmatch.cc
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@ -2,6 +2,7 @@
#include "kernel/register.h" #include "kernel/register.h"
#include "kernel/rtlil.h" #include "kernel/rtlil.h"
#include "kernel/sigtools.h" #include "kernel/sigtools.h"
#include "kernel/consteval.h"
#include "kernel/utils.h" #include "kernel/utils.h"
#include <algorithm> #include <algorithm>
@ -78,95 +79,48 @@ uint64_t p_class(int k, uint64_t lut)
bool derive_module_luts(Module *m, std::vector<uint64_t> &luts) bool derive_module_luts(Module *m, std::vector<uint64_t> &luts)
{ {
SigMap sigmap(m);
CellTypes ff_types; CellTypes ff_types;
ff_types.setup_stdcells_mem(); ff_types.setup_stdcells_mem();
for (auto cell : m->cells()) {
dict<SigBit, Cell*> driver;
for (auto cell : m->selected_cells()) {
if (cell->type.in(ID($specify2), ID($specify3), ID($specrule)))
continue;
if (ff_types.cell_known(cell->type)) { if (ff_types.cell_known(cell->type)) {
log("Ignoring module '%s' which isn't purely combinational.\n", log_id(m)); log("Ignoring module '%s' which isn't purely combinational.\n", log_id(m));
return false; return false;
} }
if (!cell->type.in(ID($_NOT_), ID($_AND_)))
log_error("Unsupported cell in module '%s': %s of type %s\n",
log_id(m), log_id(cell), log_id(cell->type));
driver[sigmap(cell->getPort(ID::Y))] = cell;
} }
TopoSort<Cell*> sort; SigSpec inputs = module_inputs(m);
for (auto cell : m->cells()) SigSpec outputs = module_outputs(m);
if (cell->type.in(ID($_NOT_), ID($_AND_))) { int ninputs = inputs.size(), noutputs = outputs.size();
sort.node(cell);
SigSpec inputs = cell->type == ID($_AND_) if (ninputs > 6) {
? SigSpec({cell->getPort(ID::B), cell->getPort(ID::A)}) log_warning("Skipping module %s with more than 6 inputs bits.\n", log_id(m));
: cell->getPort(ID::A); return false;
for (auto bit : sigmap(inputs))
if (driver.count(bit))
sort.edge(driver.at(bit), cell);
} }
if (!sort.sort()) luts.clear();
log_error("Module %s contains combinational loops.\n", log_id(m)); luts.resize(noutputs);
dict<SigBit, uint64_t> states; ConstEval ceval(m);
states[State::S0] = 0; for (int i = 0; i < 1 << ninputs; i++) {
states[State::S1] = ~(uint64_t) 1; ceval.clear();
for (int j = 0; j < ninputs; j++)
ceval.set(inputs[j], (i & (1 << j)) ? State::S1 : State::S0);
for (int j = 0; j < noutputs; j++) {
SigSpec bit = outputs[j];
{ if (!ceval.eval(bit)) {
uint64_t sieves[6] = { log("Failed to evaluate output '%s' in module '%s'.\n",
0xaaaaaaaaaaaaaaaa, log_signal(outputs[j]), log_id(m));
0xcccccccccccccccc, return false;
0xf0f0f0f0f0f0f0f0, }
0xff00ff00ff00ff00,
0xffff0000ffff0000,
0xffffffff00000000,
};
SigSpec inputs = sigmap(module_inputs(m)); log_assert(ceval.eval(bit));
if (inputs.size() > 6) {
log_warning("Skipping module %s with more than 6 inputs bits.\n", log_id(m));
return false;
}
for (int i = 0; i < inputs.size(); i++) if (bit[0] == State::S1)
states[inputs[i]] = sieves[i] & ((((uint64_t) 1) << (1 << inputs.size())) - 1); luts[j] |= 1 << i;
}
for (auto cell : sort.sorted) {
if (cell->type.in(ID($specify2), ID($specify3), ID($specrule)))
continue;
if (cell->type == ID($_AND_)) {
SigSpec a = sigmap(cell->getPort(ID::A));
SigSpec b = sigmap(cell->getPort(ID::B));
if (!states.count(a) || !states.count(b))
log_error("Cell %s in module %s sources an undriven wire!",
log_id(cell), log_id(m));
states[sigmap(cell->getPort(ID::Y))] = \
states.at(a) & states.at(b);
} else if (cell->type == ID($_NOT_)) {
SigSpec a = sigmap(cell->getPort(ID::A));
if (!states.count(a))
log_error("Cell %s in module %s sources an undriven wire!",
log_id(cell), log_id(m));
states[sigmap(cell->getPort(ID::Y))] = ~states.at(a);
} else {
log_abort();
} }
} }
for (auto bit : module_outputs(m)) {
if (!states.count(sigmap(bit)))
log_error("Output port %s in module %s is undriven!",
log_signal(bit), log_id(m));
luts.push_back(states.at(sigmap(bit)));
}
return true; return true;
} }
@ -184,10 +138,9 @@ struct CellmatchPass : Pass {
log("former to instances of the latter. This techmap rule is saved in yet another\n"); log("former to instances of the latter. This techmap rule is saved in yet another\n");
log("design called '$cellmatch_map', which is created if non-existent.\n"); log("design called '$cellmatch_map', which is created if non-existent.\n");
log("\n"); log("\n");
log("This pass restricts itself to combinational modules which must be modeled with an\n"); log("This pass restricts itself to combinational modules. Modules are functionally\n");
log("and-inverter graph. Run 'aigmap' first if necessary. Modules are functionally\n");
log("equivalent as long as their truth tables are identical upto a permutation of\n"); log("equivalent as long as their truth tables are identical upto a permutation of\n");
log("inputs and outputs. The number of inputs is limited to 6.\n"); log("inputs and outputs. The supported number of inputs is limited to 6.\n");
log("\n"); log("\n");
} }
void execute(std::vector<std::string> args, RTLIL::Design *d) override void execute(std::vector<std::string> args, RTLIL::Design *d) override